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Author SHA1 Message Date
Lioncash e1ed160768 test_arm_disassembler: More tests 
Adds tests for
- Half-word multiply and multiply accumulate instructions
- Multiply and multiply accumulate instructions
- Synchronization primitive instructions
 2016-08-28 22:06:52 +01:00
Lioncash d164184b1e test_arm_disassembler: Add more data processing instruction tests 2016-08-28 20:28:32 +01:00
MerryMage 59a8e14d1c reg_alloc: Correct OpArg::setBit for Reg 2016-08-26 15:23:38 +01:00
MerryMage ed3a686d1d Implement public header files 2016-08-26 00:44:50 +01:00
MerryMage 130b5510a6 tests/fuzz_arm: Fix MSVC conversion warnings 2016-08-25 17:46:22 +01:00
MerryMage 3caf31d19c skyeye: Fix MSVC conversion warnings 2016-08-25 17:43:59 +01:00
MerryMage ec4c91a92b skyeye: Disable MSVC warning C4200 2016-08-25 17:38:17 +01:00
Lioncash 0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage 7d181f46ce fuzz_arm: Print more than one IR basic block on failure 2016-08-25 13:00:46 +01:00
MerryMage 8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash 1bedd3bd7f CMakeLists: Clean up 
Moves functions out of the main CMakeLists file into module files that
can just be included whenever necessary. This also uses the CMake
provided variables for enforcing compiler requirements.
 2016-08-22 15:55:39 +01:00
MerryMage 74246cc3bf tests/fuzz_arm: Randomize rounding mode in initial_fpscr 2016-08-22 15:54:22 +01:00
MerryMage f014f3b7d4 tests/fuzz_arm: Update FPSCR in InterpreterFallback 2016-08-22 15:54:21 +01:00
MerryMage 7a8dd9532d skyeye: Read-after-write in SMLA 
In the case when RD === RN, RD was updated before AddOverflow was called
to check for an overflow, resulting in an incorrect state of the Q flag.

This is reapplying a patch from f12578b9ab
that was lost during the 20e253ece2 update
 2016-08-22 15:54:17 +01:00
MerryMage 20e253ece2 tests/skyeye_interpreter: Update Skyeye (22-08-1016) 
Matches the version of Skyeye in citra commit
7b4dcacbb2006de6483e982b21956a8f3098aa1d
 2016-08-22 14:07:54 +01:00
Tillmann Karras dad7724b86 TranlateArm: implement remaining multiplies 
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
 2016-08-19 01:08:38 +01:00
Tillmann Karras f12578b9ab skyeye: fix read-after-write conflicts 2016-08-19 01:08:29 +01:00
MerryMage 4acc481463 translate_arm/load_store: Handle unpredictable instructions 
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
 2016-08-19 00:59:02 +01:00
Lioncash 841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
bunnei 30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
bunnei 8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei 4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei 127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei 86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode 2016-08-10 16:43:37 +01:00
bunnei 8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage b3bb1d5048 Tests: Tidy up ARM fuzz tests 2016-08-07 21:55:38 +01:00
MerryMage 4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage 1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00
MerryMage 3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00
MerryMage a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
Tillmann Karras 55204a80d0 Implement SMMLA, SMMLS, SMMUL 2016-08-06 21:17:11 +01:00
Tillmann Karras 81d9d4b012 Add Subv's sign/zero extension tests 2016-08-06 21:17:11 +01:00
Tillmann Karras a281fcc744 Fix printf 2016-08-06 21:17:11 +01:00
MerryMage 9ab7626374 Tests/VFP: Add tests for VADD.F32 2016-08-06 20:03:15 +01:00
MerryMage 4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
bunnei a5e2116e12 fuzz_arm: Log write records on failure. 2016-08-05 20:04:57 -04:00
MerryMage 640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage 6f6f60c61b tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined 2016-08-05 16:04:16 +01:00
Tillmann Karras eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
Tillmann Karras a97668ead4 Simplify ARM fuzz tests 2016-08-05 02:09:30 +01:00
Tillmann Karras 023643b4fa Disable load/store tests for now 
I don't feel like debugging that right now.
 2016-08-05 02:09:27 +01:00
Tillmann Karras ab383b4be5 Break tests by fixing them 2016-08-05 02:08:41 +01:00
Tillmann Karras af27ef8d6c Optionally disassemble x86_64 code using LLVM 2016-08-05 02:08:41 +01:00
Tillmann Karras dacaeadb6a Raise SIGTRAP on non-Windows 2016-08-03 00:44:08 +01:00
Tillmann Karras 61eddbd1fa Fix Linux build 2016-08-03 00:44:08 +01:00
MerryMage 64c17a2489 tests/FuzzArm: Print out IR upon failure 2016-08-02 13:48:06 +01:00
MerryMage 93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage 5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
Merry 95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage 95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage 3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
Subv fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv 426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. 
These tests do not test the behavior of writing to the PC.
 2016-07-18 16:13:02 -05:00
Subv c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00
MerryMage 2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
MerryMage dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
Subv 0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
MerryMage 866dce0f23 tests/Thumb: Add revsh (thumb) test 2016-07-16 19:22:57 +01:00
MerryMage 22b1bd7cc7 tests/Skyeye: Fix thumb REVSH translation 2016-07-16 19:22:09 +01:00
MerryMage 4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage 181f78f36e Common: Remove src/common/logging/log.* 2016-07-14 14:55:08 +01:00
MerryMage 07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage 672ffb93d0 frontend/translator: Skeleton for Arm translator 2016-07-14 13:28:20 +01:00
MerryMage 8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage 60455f9bbc tests/fuzz_thumb: Fuzz instructions that may change the PC 2016-07-12 10:58:57 +01:00
MerryMage 65d27f3486 tests: Add some Arm tests 2016-07-12 09:12:56 +01:00
MerryMage 1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage d92a771e3c tests/fuzz_thumb: Implement verification of memory writes 2016-07-10 13:29:15 +08:00
MerryMage 8920ce79b9 Implement thumb_CMP_reg_t2 2016-07-10 12:23:16 +08:00
MerryMage 3f7290db16 tests/fuzz_thumb: Change how test instructions are generated (Introduce InstructionGenerator struct) 2016-07-10 12:17:02 +08:00
MerryMage 0a1f153805 tests/fuzz_thumb: Don't poison memory as that slows down tests tremendously 2016-07-08 21:43:28 +08:00
MerryMage 8a0511d297 Implement thumb1_AND_reg 2016-07-08 17:44:53 +08:00
MerryMage e5f6450a24 Start implementing Thumb disassembler 2016-07-07 21:51:47 +08:00
MerryMage f31b530703 Fuzz thumb instructions 2016-07-07 19:01:47 +08:00
MerryMage 5711e62419 Implement terminal instructions 2016-07-07 17:53:09 +08:00
MerryMage 14388ea690 Proper implementation of Arm::Translate 2016-07-04 21:37:50 +08:00
MerryMage d743adf518 Reorganisation, Import Skyeye, This is a mess 2016-07-04 17:22:11 +08:00