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2373 commits 1 branch 0 tags 34 MiB
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2038 commits

Author SHA1 Message Date
Wunkolo c2d5f6da90 block_of_code: Add HasAVX512_Icelake 
Detect AVX512 feature support up to the [Icelake-level featureset](https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512)
 2020-09-19 15:20:40 +01:00
Lioncash 0e1112b7df Revert "basic_block: Mark move constructor and assignment as noexcept" 
This reverts commit 4f12e86ebb.

Big fan of MSVC preventing standard behavior.
 2020-08-14 16:49:40 -04:00
Lioncash 889635d17d general: Resolve -Wmissing-prototypes warnings 2020-08-14 14:50:09 -04:00
Lioncash 68fea20020 common/assert: Resolve several -Wextra-semi warnings 
Resolves 200+ warnings.
 2020-08-14 14:45:53 -04:00
Lioncash 4f12e86ebb basic_block: Mark move constructor and assignment as noexcept 
Allows the type to play nicely with standard library facilities better
(also we shouldn't be throwing in move operations to begin with).
 2020-08-14 14:38:28 -04:00
Lioncash 34f4d99454 block_of_code: Remove unused variables in GenRunCode() 
These aren't used, so they can be removed.
 2020-08-14 14:35:17 -04:00
Lioncash 29d1758923 ir_matcher: Add missing header guard 2020-08-14 14:32:34 -04:00
MerryMage 6bbc53839f Unsafe Optimization: Extend Unsafe_UnfuseFMA to all FMA-related instructions 2020-07-12 12:45:12 +01:00
MerryMage d05d95c132 Improve documentation of unsafe optimizations 2020-07-12 12:41:11 +01:00
MerryMage 82417da780 emit_x64{_vector}_floating_point: Add unsafe optimizations for RSqrtEstimate and RecipEstimate 2020-07-11 14:05:57 +01:00
MerryMage 761e95eec0 A64: Add unsafe_optimizations option 
* Strength reduce FMA unsafely
 2020-07-06 21:02:30 +01:00
MerryMage 82868034d3 A32/ASIMD: Ensure decoder table is correct 
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
 2020-07-05 18:45:42 +01:00
MerryMage 3c742960a9 simd_three_same: Ensure zero in upper for PairedMinMaxOperation 2020-07-04 11:25:36 +01:00
MerryMage 735738c7b6 A32: Implement ASIMD VPMAX, VPMIN (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage 88e74cb2ba A32: Implement ASIMD VPMAX, VPMIN (integer) 2020-07-04 11:04:10 +01:00
MerryMage d9914b1d51 simd_permute: Implement VectorUnzip with deinterleave lower 2020-07-04 11:04:10 +01:00
MerryMage f35aaa017c IR: Add VectorDeinterleave{Even,Odd}Lower 2020-07-04 11:04:10 +01:00
MerryMage df477c46c2 asimd_load_store_structures: VST1 undef correction 2020-07-04 11:04:10 +01:00
MerryMage 4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage 3eed024caf asimd_three_same: Ignore Q=1 for VPADD (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage 896cb46c89 asimd_*: Standardize order of n and m to reduce confusion 2020-07-04 11:04:10 +01:00
MerryMage 4b8a781c04 emit_x64_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
MerryMage 7022281a0b emit_x64_vector_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
Merry 4f967387c0 asimd_three_regs: Reimplement asimd_VMLAL in terms of WideInstruction 2020-06-27 13:06:46 +01:00
Merry 7997404ee7 A32: Implement ASIMD V{ADD,SUB}{W,L} 2020-06-27 12:58:47 +01:00
Merry 868bd00ab5 A32: Rearrange translators for ASIMD Three Registers 
* Separate Three Registers with Different Lengths from Same Lengths decoders
 2020-06-27 11:15:07 +01:00
Merry b1ff971a92 backend/x64: Temporarily avoid use of DefineValue(Argument&) 
Issues with inappropriate values in upper bits of values
 2020-06-27 10:52:59 +01:00
MerryMage 8a1f106dba decoder/asimd: Correct names of scalar exceptions 2020-06-25 17:40:11 +01:00
MerryMage 495f58eed8 A32: Implement ASIMD VSHLL 2020-06-24 23:47:13 +01:00
MerryMage ed48a9d7d5 A32: Implement VFPv5 VRINTX 2020-06-24 22:31:58 +01:00
MerryMage 46445d0866 A64: Remove NaN accuracy setting 
Always do accuracte NaN handling.
 2020-06-24 22:26:10 +01:00
Lioncash b5df8d1ef8 A32: Implement ASIMD VQDMULL (scalar) 2020-06-23 18:19:42 +01:00
Lioncash 20a2bf29fc A32: Implement ASIMD VQRDMULH (scalar) 2020-06-23 18:19:42 +01:00
Lioncash ab5efe8632 A32: Implement ASIMD VQDMULH (scalar) 2020-06-23 18:19:42 +01:00
MerryMage 2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed 2020-06-22 22:54:38 +01:00
MerryMage 3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage 48b2ffdde9 A32: Implement ASIMD VQMOVUN, VQMOVN 2020-06-22 20:02:52 +01:00
MerryMage 52b8039367 A32: Implement VFPv5 VRINT{R,Z} 2020-06-22 19:35:32 +01:00
MerryMage 47bc99ad9f asimd_load_store_structures: Fix 2-byte aligned vld1.16 
Previously incorrectly undefined
 2020-06-22 18:46:22 +01:00
Lioncash dd8d5497da A32: Implement ASIMD VQRDMULH 2020-06-22 17:31:57 +01:00
Lioncash 0b7a111b54 A32: Implement ASIMD VQDMULH 2020-06-22 17:31:57 +01:00
Lioncash 39488e4aad A32: Implement ASIMD VRSHRN 2020-06-21 23:15:43 +01:00
Lioncash 86b0e5c1c5 A32: Implement ASIMD VQSHRN 2020-06-21 23:15:43 +01:00
Lioncash 85222e3e65 A32: Implement ASIMD VQSHRUN 
We can leverage ShiftRightNarrowing() to implement this.
 2020-06-21 23:15:43 +01:00
MerryMage 562a98bcf9 A32: Implement ASIMD VCVT (between floating-point and fixed-point) 2020-06-21 20:23:40 +01:00
MerryMage 6f56043a73 A32: Implement ASIMD VFMA, VFMS 2020-06-21 20:21:53 +01:00
Lioncash aa0358d324 A32: Implement ASIMD VMLAL/VMLSL (integer) 2020-06-21 20:03:19 +01:00
Lioncash eab26b404a A32: Implement ASIMD VABAL 2020-06-21 20:01:08 +01:00
Lioncash 98581839ca A32: Implement ASIMD VABDL 2020-06-21 19:55:00 +01:00
MerryMage db85e7ced5 asimd: Add missing three registers of different lengths instructions 2020-06-21 19:54:32 +01:00