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2212 commits 1 branch 0 tags 34 MiB
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60 commits

Author SHA1 Message Date
Lioncash 93ed3441b7 A32: Implement ASIMD VCLS/VCLZ/VCNT 2020-06-16 09:54:28 +01:00
Lioncash 15b3de95e4 A32: Implement VNEG 2020-06-16 01:53:21 +01:00
MerryMage f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage 16ff880f8f A32: Implement ASIMD VQADD 2020-05-30 16:09:37 +01:00
MerryMage 3a50d444dc A32: Implement ASIMD VHSUB 2020-05-28 22:29:00 +01:00
MerryMage 205e6c5a56 A32: Implement ASIMD VRHADD 2020-05-28 22:29:00 +01:00
MerryMage 946eb03a3b A32: Implement ASIMD VHADD 2020-05-28 22:29:00 +01:00
Lioncash fc112e61f2 A32: Implement ASIMD modified immediate functions 
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
 2020-05-24 23:55:47 +01:00
Lioncash 659d78c9c4 A32: Implement ASIMD VSWP 
A trivial one to implement, this just swaps the contents of two
registers in place.
 2020-05-22 19:43:24 +01:00
MerryMage d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) 2020-05-17 17:01:39 +01:00
Lioncash f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash 4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash 67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash 1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash 64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash 0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00
MerryMage 1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
MerryMage 59db2c191a VFPv3: Implement VMOV (immediate) 2020-05-10 15:09:37 +01:00
MerryMage 3c86d58064 VFPv4: Implement VCVTB, VCVTT 2020-05-10 14:45:18 +01:00
MerryMage 010fab9a0e VFPv4: Implement VFMA, VFMS 2020-05-10 14:20:11 +01:00
MerryMage 8e97b10acb VFPv4: Implement VFNMS, VFNMA 2020-05-10 14:14:03 +01:00
MerryMage 6df660c889 fuzz_arm: Ensure all instructions are fuzzed 
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
 2020-05-10 13:57:39 +01:00
MerryMage 9a38c7324f A32: Add decoders for remaining v7 instructions 2020-05-10 10:50:34 +01:00
MerryMage a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
Merry fd6222f0a1 Merge pull request #500 from lioncash/cbz 
A32: Implement Thumb-1's CBZ/CBNZ instructions
 2020-04-22 21:04:21 +01:00
Lioncash 03e6899fd7 A32: Implement Thumb-1's CBZ/CBNZ instructions 
Introduced in ARMv6T2, this allows for short forward branches.
 2020-04-22 21:02:47 +01:00
Lioncash 106c8c2473 A32: Implement ARM-mode MOVW 
Introduced to the ISA in ARMv6T2
 2020-04-22 21:02:47 +01:00
Lioncash 9935f3aa28 A32: Implement Thumb-1 variant of SEVL 
While we're at it, also add the Thumb-2 encoding to the encoding table
to make sure it isn't forgotten about in the future.
 2020-04-22 21:02:47 +01:00
Lioncash 9a097e307f A32: Implement the ARM-mode variant of SEVL 2020-04-22 21:02:47 +01:00
Lioncash e89ca42048 A32: Implement Thumb-1 variant of YIELD 2020-04-22 21:02:47 +01:00
Lioncash ebab7ede55 A32: Implement Thumb-1 variant of WFI 2020-04-22 21:02:47 +01:00
Lioncash b4110af22a A32: Implement Thumb-1 variant of WFE 2020-04-22 21:02:47 +01:00
Lioncash 57675fe592 A32: Implement Thumb-1 variant of SEV 2020-04-22 21:02:47 +01:00
Lioncash 64879396f6 A32: Implement Thumb-1 variant of NOP 2020-04-22 21:02:47 +01:00
Merry 81b908b077 Merge pull request #495 from lioncash/bkpt 
A32: Implement Thumb-16's variant of BKPT
 2020-04-22 21:02:47 +01:00
Lioncash b17a5d3365 A32: Implement Thumb-16's variant of BKPT 2020-04-22 21:02:47 +01:00
Lioncash 0fa0bca22a A32: Handle different variants of PLD 2020-04-22 21:02:47 +01:00
Merry 30d28029a8 Merge pull request #492 from lioncash/vfp 
A32: Rename vfp2-related files to vfp
 2020-04-22 21:02:47 +01:00
Lioncash 97277c598b A32: Rename vfp2-related files to vfp 
Now that we fuzz against Unicorn, we aren't just restricted to VFPv2.
VFPv3 and VFPv4 facilities can now be implemented. This renames
constructs mentioning VFPv2 to just refer to VFP.
 2020-04-22 21:02:46 +01:00
Lioncash e37689315d A32: Implement ARM-mode CRC32 instructions 
Implements the ARM-mode variants of the CRC32 instructions introduced
within ARMv8. This is also one of the instruction cases where there is
UNPREDICTABLE behavior that is constrained (we must do one of the
options indicated by the reference manual).

In both documented cases of constrained unpredictable behavior, we treat
the instructions as unpredictable in order to allow library users to
hook the unpredictable exception to provide the intended behavior they
desire.
 2020-04-22 21:02:46 +01:00
Lioncash 8316d231e9 A32: Implement barrier instructions introduced in ARMv7 
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
 2020-04-22 21:02:46 +01:00
Lioncash 7fc3bd689d A32: Implement ARM-mode MLS 2020-04-22 21:02:46 +01:00
Lioncash 8b338b7def A32: Implement ARM-mode MOVT 2020-04-22 21:02:46 +01:00
Lioncash 877fa0f8c3 A32: Implement ARM-mode SBFX 2020-04-22 21:02:46 +01:00
Lioncash 47218ee65d A32: Implement ARM-mode UBFX 2020-04-22 21:02:46 +01:00
Lioncash 2970b34e3c A32: Implement ARM-mode BFI 2020-04-22 21:02:46 +01:00
Lioncash fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00