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42 commits

Author SHA1 Message Date
Lioncash 75fd4eaaaa emit_x64_vector: Get rid of some magic numbers in loop bounds 2020-04-22 20:46:17 +01:00
Lioncash 7b80ac25eb emit_x64_vector: Generify variable shift functions 2020-04-22 20:46:17 +01:00
Lioncash 64b1f2d468 ir: Add opcode for reversing bits in a vector 2020-04-22 20:46:15 +01:00
Lioncash e33dcce14a ir: Add opcodes for performing vector absolute values 2020-04-22 20:46:15 +01:00
MerryMage 3472f371df IR: Implement VectorExtract, VectorExtractLower IR instructions 2020-04-22 20:46:15 +01:00
Lioncash ad5cf584ce ir: Add opcodes for performing vector unsigned absolute differences 2020-04-22 20:46:15 +01:00
Lioncash 701f43d61e IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2020-04-22 20:46:15 +01:00
Lioncash b8d5765f9b emit_x64_vector: Fix typo in VectorShuffleImpl 
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
 2020-04-22 20:46:15 +01:00
Lioncash 6b0010c940 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2020-04-22 20:46:15 +01:00
MerryMage 147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage 710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage 1dfce0894d constant_pool: Add frame parameter 2020-04-22 20:46:14 +01:00
MerryMage 47c0ad0fc8 IR: Implement Vector{Max,Min}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage f4775910f5 IR: Implement VectorGreaterSigned 2020-04-22 20:46:14 +01:00
MerryMage eae518a338 IR: Implement VectorSignExtend 2020-04-22 20:46:14 +01:00
MerryMage 851fc83445 emit_x64_vector: EmitOneArgumentFallback 2020-04-22 20:46:14 +01:00
MerryMage 303088a51e IR: Implement VectorPopulationCount 2020-04-22 20:46:14 +01:00
MerryMage bf2cd92da9 emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64 2020-04-22 20:46:14 +01:00
MerryMage b062266b8e emit_x64_vector: More explicit lambda decay 2020-04-22 20:46:14 +01:00
MerryMage b6de612e01 IR: Implement VectorMultiply 2020-04-22 20:46:14 +01:00
MerryMage 90a053a5e4 emit_x64_vector: Order alphabetically 2020-04-22 20:46:14 +01:00
MerryMage 715ae1c229 IR: Implement VectorArithmeticShiftRight 2020-04-22 20:46:14 +01:00
MerryMage 132c783320 IR: Implement VectorNarrow 2020-04-22 20:46:13 +01:00
MerryMage 69de50a878 emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage cbc9f361b0 IR: Implement VectorSub 2020-04-22 20:46:13 +01:00
MerryMage b22c5961f9 IR: Implement VectorLogicalShiftRight 2020-04-22 20:46:13 +01:00
MerryMage 59ace60b03 IR: Implement VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage f6247125c0 IR: Implement VectorLogicalShiftLeft{8,16,32,64} 2020-04-22 20:46:13 +01:00
MerryMage 15e8231f24 opcodes: Sort vector IR opcodes alphabetically 2020-04-22 20:46:13 +01:00
Lioncash 35a29a9665 A64: Implement ZIP1 2020-04-22 20:46:13 +01:00
MerryMage 68f46c8334 backend_x64: Use a reference to BlockOfCode instead of a pointer 2020-04-22 20:46:13 +01:00
MerryMage 6414736a8d emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1 
This bug wasn't discovered earlier because we previously only used index == 0.
 2020-04-22 20:46:13 +01:00
MerryMage ebfc51c609 IR: Implement VectorSetElement{8,16,32,64} 2020-04-22 20:46:13 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
Fernando Sahmkow e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage 285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage 793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage db30e02ac8 emit_x64: Extract BlockRangeInformation, remove template parameter 2020-04-22 20:44:36 +01:00
MerryMage eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00