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86 commits

Author SHA1 Message Date
BreadFish64 2a65442933 Backend: Create "backend" folder 
similar to the "frontend" folder
 2020-04-22 20:53:46 +01:00
MerryMage a12afd1065 reg_alloc: Add the ability to Release an allocation early 2020-04-22 20:53:45 +01:00
MerryMage 89d08c7d61 IR: Add VectorTable and VectorTableLookup IR instructions 2020-04-22 20:53:45 +01:00
Lioncash c41b5a3492 x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 
This way if the number ever changes, we don't need to change the type in
other places.
 2020-04-22 20:46:23 +01:00
MerryMage e9ab7f7664 reg_alloc: Do a UseScratch if a Use destination is too small 2020-04-22 20:46:23 +01:00
MerryMage 1dfce0894d constant_pool: Add frame parameter 2020-04-22 20:46:14 +01:00
MerryMage 84f1c9b7f4 reg_alloc: Only exchange GPRs 2020-04-22 20:46:14 +01:00
MerryMage 6c4773e85b abi: Add RAX to ABI_ALL_CALLER_SAVE 2020-04-22 20:46:14 +01:00
MerryMage 68f46c8334 backend_x64: Use a reference to BlockOfCode instead of a pointer 2020-04-22 20:46:13 +01:00
MerryMage d7044bc751 assert: Use fmt in ASSERT_MSG 2020-04-22 20:46:12 +01:00
MerryMage b2d99eddc6 EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 2020-04-22 20:46:12 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage 4ce9c65cfb reg_alloc: Use std::exchange 2020-04-22 20:44:38 +01:00
MerryMage 28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage 5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage 9a812b0c61 reg_alloc: GetBitWidth: Add UNREACHABLE 2020-04-22 20:42:46 +01:00
MerryMage fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage 6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage e4615a4562 emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2020-04-22 20:42:45 +01:00
MerryMage 5a1d88c5dc A64: Implement pcrel 2020-04-22 20:42:45 +01:00
MerryMage 9d15e0a8e1 Final A32 refactor 2020-04-22 20:39:27 +01:00
MerryMage 7bf421dd38 Rename JitState to A32JitState 2020-04-22 20:38:31 +01:00
MerryMage 80c56aa89d Remove unnecessary use of boost::make_optional 
Closes #119.
 2020-04-22 20:26:12 +01:00
MerryMage 639f7cfd2d reg_alloc: Add IsLastUse optimization for UseScratch 2020-04-22 20:26:12 +01:00
MerryMage 6b122751fe reg_alloc: Remove reliance on IR::Inst::DecrementRemainingUses 2020-04-22 20:26:12 +01:00
MerryMage 29471be317 Standardize location of storage-class specifiers: Place at beginning of declarations 
Justification: C99 specifies that doing otherwise is an obsolescent feature.
 2017-09-29 01:23:45 +01:00
MerryMage 1613846ab0 reg_alloc: Handle XMM registers in LoadImmediate 2017-08-16 23:11:05 +01:00
MerryMage 9ac890c62d reg_alloc: Fix for LLVM's interpretation of the System V ABI 
This aspect of the System V ABI is under-defined. LLVM choses a
different interpretation from GCC and ICC.

Most other compilers assume the callee is responsible zero-ing the
upper bits of the register if necessary. LLVM assumes the caller
has zero-extended the register.

This is a quick fix for this problem until zext-tracking is
implemented.
 2017-04-08 22:12:37 +01:00
MerryMage 92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage 135346eb2e reg_alloc: Move implementations out of header 2017-02-26 23:30:39 +00:00
MerryMage 184db36caf reg_alloc: Call DecrementRemainingUses in only one place 2017-02-26 23:30:38 +00:00
MerryMage 51fc9fec05 reg_alloc: Reorganize 2017-02-26 23:30:37 +00:00
MerryMage cf93ab3d31 reg_alloc: Remove old register allocator interface 2017-02-26 23:12:26 +00:00
MerryMage 08a467bf9a emit_x64: Port to new register allocator interface 2017-02-26 23:12:25 +00:00
MerryMage f883bad2cc reg_alloc: New register allocation interface 2017-02-26 21:37:35 +00:00
MerryMage 13ac0c234e reg_alloc: Differentiate between ReadLock and WriteLock 2017-02-26 21:37:34 +00:00
MerryMage 6c3df057fa reg_alloc: Remove unused functions 2017-02-26 21:37:33 +00:00
MerryMage 1ee4c07f14 reg_alloc: Reimplement ScratchHostLocReg 2017-02-26 21:37:32 +00:00
MerryMage 640faab8a7 reg_alloc: UseHostLoc is no longer necessary 2017-02-26 21:37:30 +00:00
MerryMage 9518bbe06e reg_alloc: Reimplement UseScratchHostLocReg 2017-02-26 21:37:29 +00:00
MerryMage e1d8238c50 reg_alloc: Stub UseOpArg 2017-02-26 21:37:27 +00:00
MerryMage 2b078152e7 reg_alloc: Reimplement UseHostLocReg 2017-02-26 21:37:26 +00:00
MerryMage aefe550428 reg_alloc: Remove the Def concept from register allocator internals 2017-02-26 21:37:25 +00:00
MerryMage 65cccf070e reg_alloc: Properly encapsulate HostLocInfo 2017-02-26 21:37:24 +00:00
MerryMage f2fe376fc6 Support 64-bit immediates 2016-12-03 11:29:50 +00:00
Mat M 95f34c683c reg_alloc: Remove unnecessary breaks after returns (#54) 2016-12-02 19:14:44 +00:00
Mat M de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
MerryMage 3621a925b2 reg_alloc: Register allocator related constraints belong with the rest of the register allocator 
HostLocToReg64 contained two DEBUG_ASSERTs invloving constraints that
really belonged to the register allocator.

The register allocator prevents allocation of RSP and R15 because those
are reserved for the stack pointer and the state pointer respectively.
 2016-11-30 19:42:41 +00:00
Mat M 7f9a0c3c38 Remove unnecessary explicit includes (#16) 2016-09-03 21:48:03 +01:00
Mat M 1e781d911a reg_alloc: const correctness (#8) 2016-09-02 17:30:01 +01:00