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1501 commits

Author SHA1 Message Date
Lioncash 20ffe568d0 A64: Implement RMIF 2020-04-22 20:58:11 +01:00
Lioncash 51b526e453 A64: Implement CFINV 2020-04-22 20:58:11 +01:00
Lioncash 597a8be5d5 ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2020-04-22 20:58:11 +01:00
Merry 4f937c1ee1 Merge pull request #446 from lioncash/sqshl 
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
 2020-04-22 20:58:11 +01:00
Merry d74cccbc84 Merge pull request #445 from lioncash/sqrt 
A64: Implement single and double-precision vector variant of FSQRT
 2020-04-22 20:58:11 +01:00
Merry 6d7e7c3269 Merge pull request #443 from lioncash/flag 
A64: Rearrange flag format/manipulation instructions
 2020-04-22 20:58:11 +01:00
Merry 5d01f1b462 Merge pull request #441 from lioncash/constexpr 
common/bit_util: Mark a few functions as constexpr
 2020-04-22 20:58:11 +01:00
Merry 743c52fdc5 Merge pull request #440 from lioncash/include 
common/fp: Remove unnecessary includes
 2020-04-22 20:58:11 +01:00
Lioncash 17aea0b997 A64: Implement UQSHL (register)'s scalar variant 
This can be implemented in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00
Lioncash 54e0b487f3 A64: Rearrange flag format/manipulation instructions 
Gives these instructions better categorical labeling.
 2020-04-22 20:58:10 +01:00
Lioncash 88d1977cb9 common/bit_util: Make a few functions as constexpr 
These four functions can be made constexpr with no issue.
 2020-04-22 20:58:10 +01:00
Lioncash f33e5939b7 common/fp: Remove unnecessary includes 2020-04-22 20:58:10 +01:00
Lioncash 302f56b36a A64: Fall back to interpreting for FCADD and FCMLA half-precision variants 
Rather than straight-up treating them as undefined, we can fall back to an
interpreter in this case.
 2020-04-22 20:58:10 +01:00
Lioncash 35ddf68ad5 A64: Implement SQSHL (register)'s scalar variant 
We can implement this in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash 5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash 36027ebef5 frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2020-04-22 20:58:10 +01:00
Merry 40b081438a Merge pull request #439 from lioncash/fcmla 
A64: Implement FCADD and FCMLA
 2020-04-22 20:58:10 +01:00
Merry d91192681a Merge pull request #438 from lioncash/fmulx 
A64: Implement scalar double/single precision FMULX (by element)
 2020-04-22 20:58:10 +01:00
Lioncash ed29ef8cca A64: Implement FCMLA 2020-04-22 20:58:10 +01:00
Merry 9f11720a69 Merge pull request #437 from lioncash/frecpx 
A64: Implement FRECPX (single, double precision)
 2020-04-22 20:58:10 +01:00
Lioncash bdcea0b0dc A64: Implement scalar double/single precision FMULX (by element) 2020-04-22 20:58:10 +01:00
Lioncash 5ce17574f9 A64: Implement FCADD 2020-04-22 20:58:10 +01:00
Merry 34d917f34e Merge pull request #436 from lioncash/no-alloc 
A64: Implement LDNP/STNP
 2020-04-22 20:58:10 +01:00
Lioncash e44730ba6d A64: Implement FRECPX (single, double precision) 2020-04-22 20:58:10 +01:00
Lioncash bfaeb08d3c A64: Implement LDNP/STNP 
LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
 2020-04-22 20:58:10 +01:00
Lioncash 9cf3c25811 frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents 2020-04-22 20:58:10 +01:00
Merry dbf47db713 Merge pull request #434 from lioncash/format 
A32/translate_arm: Formatting/tidying up
 2020-04-22 20:58:10 +01:00
Lioncash b168c2a9f9 common/fp/op: Add operations for floating-point reciprocal exponents 2020-04-22 20:58:10 +01:00
Lioncash 05a6ab691d translate_arm/coprocessor: Minor tidying up 2020-04-22 20:58:10 +01:00
Lioncash 1e32a09c03 translate_arm/vfp2: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash e209b31073 translate_arm/synchronization: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash 9514e3602e translate_arm/status_register_access: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash c6aa1a708a translate_arm/saturated: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash a72813599a translate_arm/reversal: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash 7be56e6b67 translate_arm/parallel: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash 3c00a616d6 translate_arm/packing: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash c711188f46 translate_arm/multiply: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash c8dad40d81 translate_arm/misc: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash a7bf5ff77d translate_arm/load_store: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash 2e180a7f14 backend/x64/a32_interface: Mark Context move constructor and move assignment as noexcept 
Provides a more "correct" move constructor/assignment operator, since
these relevant functions shouldn't throw exceptions.

Has the benefit of playing nicely with std::move_if_noexcept and other
noexcept library facilities.
 2020-04-22 20:58:09 +01:00
Lioncash f4b19a7393 translate_arm/extension: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash deb9dd4acc block_of_code: Replace cast with [[maybe_unused]] in DoesCpuSupport() 2020-04-22 20:58:09 +01:00
Lioncash c2de6ecfd0 translate_arm/exception_generating: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash d8a8d3b073 translate_arm/data_processing: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash df5c51ff47 translate_arm/branch: Invert conditionals where applicable 
Allows unindenting code a bit.
 2020-04-22 20:58:09 +01:00
Lioncash 3290a9fdc2 common: Remove address_range.h 
The AddressRange structure isn't used anywhere within the codebase, so
this can be removed. Particularly because there's no real appeal/heavy
potential use of it in the future that isn't trivial to add back if
needed.
 2020-04-22 20:57:38 +01:00
Lioncash ee973f13c7 frontend/A32/ir_emitter: Mark PC() and AlignPC() as const-qualified member functions 
These don't modify instance state, so they can be const-qualified member
functions.
 2020-04-22 20:57:38 +01:00
Lioncash 3a2dd09122 frontend/A64/ir_emitter: Mark PC() and AlignPC() as const qualified member functions 
These don't actually alter any instance state.
 2020-04-22 20:57:38 +01:00
Lioncash 575ae852a9 constant_propagation_pass: Fold byte reversal opcodes where applicable 
These are reasonably trivial to fold away when applicable. We just
perform the swap and replace the instruction with the constant value.
 2020-04-22 20:57:37 +01:00