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1184 commits

Author SHA1 Message Date
MerryMage 0de37b11ad A64: Implement FMLS (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 64c2f698a2 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly 
MSVC doesn't like dealing with auto return types
 2020-04-22 20:46:22 +01:00
MerryMage 2ef59b4f03 emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused 2020-04-22 20:46:22 +01:00
MerryMage 04f325a05e IR: Implement FPVectorNeg 2020-04-22 20:46:22 +01:00
MerryMage 934132e0c5 A64: Implement FMLA (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 771a4fc20b IR: Implement FPVectorMulAdd 2020-04-22 20:46:22 +01:00
MerryMage 3218bb9890 emit_x64_vector_floating_point: Standardize naming scheme 2020-04-22 20:46:22 +01:00
MerryMage 8f72be0a02 emit_x64_floating_point: Simplify indexers 2020-04-22 20:46:22 +01:00
MerryMage 25b28bb234 emit_x64_vector_floating_point: Simplify EmitVectorOperation* 2020-04-22 20:46:22 +01:00
MerryMage 1edd0125b2 mp: rename mp.h to mp/function_info.h 2020-04-22 20:46:22 +01:00
MerryMage 0921678edb emit_x64_vector: Slightly improve ArithmeticShiftRightByte 2020-04-22 20:46:22 +01:00
MerryMage 43407c4bb4 emit_x64_vector: Simplify VectorShuffleImpl 2020-04-22 20:46:22 +01:00
MerryMage ecbf9dbae5 IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
MerryMage f0fecf2615 A64: Implement UQSHRN, UQRSHRN (vector) 2020-04-22 20:46:22 +01:00
MerryMage 8f4c1a8558 emit_x64_vector: -0x80000000 isn't -0x80000000 2020-04-22 20:46:22 +01:00
MerryMage b455b566e7 A64: Implement UQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage e686a81612 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison 
Allows non-SSE4.1 to produce the correct FPSR.QC flag
 2020-04-22 20:46:22 +01:00
MerryMage 3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage 8ef114d48f emit_x64_vector: packusdw reqiures SSE4.1 
In EmitVectorSignedSaturatedNarrowToUnsigned32.
 2020-04-22 20:46:22 +01:00
MerryMage 712c6c1d7e A64: Implement SQSHRUN, SQRSHRUN (vector) 2020-04-22 20:46:22 +01:00
MerryMage c5722ec963 simd_shift_by_immediate: Simplify ShiftRight 2020-04-22 20:46:22 +01:00
MerryMage f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage 6918ef7360 microinstruction: Reorganize FPSCR related instruction queries 2020-04-22 20:46:22 +01:00
Lioncash a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() 
These were forgotten when the opcodes were added.
 2020-04-22 20:46:22 +01:00
Lioncash 3ca18d8a6d u128: Make Bit() a const-qualified member function 
This function doesn't modify the struct members, so it can be made
const.
 2020-04-22 20:46:22 +01:00
MerryMage b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 45dc5f74f3 A64: Implement FRSQRTE (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage b74d5520f9 A64: Implement FRSQRTS (scalar), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 506e544bfe IR: Implement FPRSqrtStepFused 2020-04-22 20:46:22 +01:00
MerryMage 6eb069e80d fp: Implement FPRSqrtStepFused 2020-04-22 20:46:22 +01:00
MerryMage b0ff35fcd1 fp: Implement FPNeg 2020-04-22 20:46:22 +01:00
MerryMage ca6774ccce process_nan: Add two operand variant 2020-04-22 20:46:22 +01:00
Lioncash ace7d2ba50 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage 66bb05fc0a emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation 2020-04-22 20:46:21 +01:00
Lioncash 070637e0f6 fp: Use a forward declaration in fused.h 
It's permissible to forward declare here, so we can do so and eliminate
a direct header dependency
 2020-04-22 20:46:21 +01:00
Lioncash 030820f649 u128: Implement comparison operators in terms of one another 
We can just implement the comparisons in terms of operator< and
implement inequality with the negation of operator==.
 2020-04-22 20:46:21 +01:00
MerryMage 76b07d6646 u128: StickyLogicalShiftRight requires special-casing for amount == 64 
In this case (128 - amount) == 64, and this invokes undefined behaviour
 2020-04-22 20:46:21 +01:00
Lioncash 49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 2020-04-22 20:46:21 +01:00
Lioncash c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage 0ce11b7b15 emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} 2020-04-22 20:46:21 +01:00
MerryMage e199887fbc fp: Implement FPMulAdd 2020-04-22 20:46:21 +01:00
MerryMage 53a8c15d12 process_nan: Add FPProcessNaNs3 2020-04-22 20:46:21 +01:00
MerryMage 1c8e93e74d block_of_code: Add SysV ABI fifth and sixth parameters 2020-04-22 20:46:21 +01:00
MerryMage 1fe8f51c54 u128: Add StickyLogicalShiftRight 2020-04-22 20:46:21 +01:00
MerryMage b0afd53ea7 u128: Add Multiply64To128 2020-04-22 20:46:21 +01:00
MerryMage 5566fab29a u128: Add u128::Bit 2020-04-22 20:46:21 +01:00
MerryMage 3e62fea003 u128: Add comparison operators 2020-04-22 20:46:21 +01:00
MerryMage f17cd6f2c5 unpacked: Use ResidualErrorOnRightShift in FPRoundBase 
Fixes a bug relating to exponents that are severely out of range.
 2020-04-22 20:46:21 +01:00
MerryMage 805428e35e fp: Remove MantissaT 2020-04-22 20:46:21 +01:00
MerryMage bda86fd167 FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate 2020-04-22 20:46:21 +01:00