mirror of
https://github.com/xenia-project/xenia.git
synced 2026-03-05 21:14:14 +01:00
824 lines
24 KiB
C++
824 lines
24 KiB
C++
/*
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "cpu/codegen/emit.h"
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#include <xenia/cpu/codegen/function_generator.h>
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#include <xenia/cpu/ppc/state.h>
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using namespace llvm;
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using namespace xe::cpu::codegen;
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using namespace xe::cpu::ppc;
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using namespace xe::cpu::sdb;
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namespace xe {
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namespace cpu {
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namespace codegen {
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int XeEmitIndirectBranchTo(
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FunctionGenerator& g, IRBuilder<>& b, const char* src, uint32_t cia,
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bool lk, uint32_t reg) {
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// TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// a normal function return that is pulling the LR from the stack that
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// it set in the prolog. If so, we can omit the dynamic check!
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// NOTE: we avoid spilling registers until we know that the target is not
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// a basic block within this function.
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Value* target;
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switch (reg) {
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case kXEPPCRegLR:
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target = g.lr_value();
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break;
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case kXEPPCRegCTR:
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target = g.ctr_value();
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break;
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default:
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XEASSERTALWAYS();
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return 1;
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}
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// Dynamic test when branching to LR, which is usually used for the return.
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// We only do this if LK=0 as returns wouldn't set LR.
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// Ideally it's a return and we can just do a simple ret and be done.
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// If it's not, we fall through to the full indirection logic.
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if (!lk && reg == kXEPPCRegLR) {
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BasicBlock* next_block = g.GetNextBasicBlock();
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BasicBlock* mismatch_bb = BasicBlock::Create(*g.context(), "lr_mismatch",
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g.gen_fn(), next_block);
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Value* lr_cmp = b.CreateICmpEQ(target, ++(g.gen_fn()->arg_begin()));
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// The return block will spill registers for us.
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b.CreateCondBr(lr_cmp, g.GetReturnBasicBlock(), mismatch_bb);
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b.SetInsertPoint(mismatch_bb);
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}
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// Defer to the generator, which will do fancy things.
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bool likely_local = !lk && reg == kXEPPCRegCTR;
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return g.GenerateIndirectionBranch(cia, target, lk, likely_local);
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}
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int XeEmitBranchTo(
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FunctionGenerator& g, IRBuilder<>& b, const char* src, uint32_t cia,
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bool lk) {
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// Get the basic block and switch behavior based on outgoing type.
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FunctionBlock* fn_block = g.fn_block();
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switch (fn_block->outgoing_type) {
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case FunctionBlock::kTargetBlock:
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{
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BasicBlock* target_bb = g.GetBasicBlock(fn_block->outgoing_address);
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XEASSERTNOTNULL(target_bb);
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b.CreateBr(target_bb);
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break;
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}
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case FunctionBlock::kTargetFunction:
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{
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// Spill all registers to memory.
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// TODO(benvanik): only spill ones used by the target function? Use
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// calling convention flags on the function to not spill temp
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// registers?
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g.SpillRegisters();
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Function* target_fn = g.GetFunction(fn_block->outgoing_function);
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Function::arg_iterator args = g.gen_fn()->arg_begin();
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Value* state_ptr = args;
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BasicBlock* next_bb = g.GetNextBasicBlock();
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if (!lk || !next_bb) {
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// Tail. No need to refill the local register values, just return.
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// We optimize this by passing in the LR from our parent instead of the
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// next instruction. This allows the return from our callee to pop
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// all the way up.
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b.CreateCall2(target_fn, state_ptr, ++args);
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b.CreateRetVoid();
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} else {
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// Will return here eventually.
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// Refill registers from state.
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b.CreateCall2(target_fn, state_ptr, b.getInt64(cia + 4));
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g.FillRegisters();
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b.CreateBr(next_bb);
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}
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break;
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}
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case FunctionBlock::kTargetLR:
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA LR: %.8X\n", cia);
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return XeEmitIndirectBranchTo(g, b, src, cia, lk, kXEPPCRegLR);
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}
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case FunctionBlock::kTargetCTR:
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA CTR: %.8X\n", cia);
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return XeEmitIndirectBranchTo(g, b, src, cia, lk, kXEPPCRegCTR);
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}
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default:
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case FunctionBlock::kTargetNone:
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XEASSERTALWAYS();
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return 1;
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}
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return 0;
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}
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XEDISASMR(bx, 0x48000000, I )(InstrData& i, InstrDisasm& d) {
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d.Init("b", "Branch", i.I.LK ? InstrDisasm::kLR : 0);
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uint32_t nia;
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if (i.I.AA) {
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nia = XEEXTS26(i.I.LI << 2);
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} else {
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nia = i.address + XEEXTS26(i.I.LI << 2);
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}
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d.AddUImmOperand(nia, 4);
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return d.Finish();
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}
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XEEMITTER(bx, 0x48000000, I )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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// if AA then
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// NIA <- EXTS(LI || 0b00)
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// else
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// NIA <- CIA + EXTS(LI || 0b00)
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// if LK then
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// LR <- CIA + 4
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uint32_t nia;
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if (i.I.AA) {
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nia = XEEXTS26(i.I.LI << 2);
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} else {
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nia = i.address + XEEXTS26(i.I.LI << 2);
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}
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if (i.I.LK) {
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g.update_lr_value(b.getInt32(i.address + 4));
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}
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return XeEmitBranchTo(g, b, "bx", i.address, i.I.LK);
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}
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XEDISASMR(bcx, 0x40000000, B )(InstrData& i, InstrDisasm& d) {
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// TODO(benvanik): mnemonics
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d.Init("bc", "Branch Conditional", i.B.LK ? InstrDisasm::kLR : 0);
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if (!XESELECTBITS(i.B.BO, 2, 2)) {
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d.AddCTR(InstrRegister::kReadWrite);
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}
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if (!XESELECTBITS(i.B.BO, 4, 4)) {
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d.AddCR(i.B.BI >> 2, InstrRegister::kRead);
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}
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d.AddUImmOperand(i.B.BO, 1);
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d.AddUImmOperand(i.B.BI, 1);
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return d.Finish();
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}
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XEEMITTER(bcx, 0x40000000, B )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3])
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// if AA then
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// NIA <- EXTS(BD || 0b00)
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// else
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// NIA <- CIA + EXTS(BD || 0b00)
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.B.LK) {
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g.update_lr_value(b.getInt32(i.address + 4));
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}
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Value* ctr_ok = NULL;
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if (XESELECTBITS(i.B.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = g.ctr_value();
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ctr = b.CreateSub(ctr, b.getInt64(1));
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g.update_ctr_value(ctr);
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// Ctr check.
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if (XESELECTBITS(i.B.BO, 1, 1)) {
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ctr_ok = b.CreateICmpEQ(ctr, b.getInt64(0));
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} else {
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ctr_ok = b.CreateICmpNE(ctr, b.getInt64(0));
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}
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}
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Value* cond_ok = NULL;
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if (XESELECTBITS(i.B.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = g.cr_value(i.B.BI >> 2);
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cr = b.CreateAnd(cr, 1 << (i.B.BI & 3));
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if (XESELECTBITS(i.B.BO, 3, 3)) {
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cond_ok = b.CreateICmpNE(cr, b.getInt64(0));
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} else {
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cond_ok = b.CreateICmpEQ(cr, b.getInt64(0));
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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if (ctr_ok && cond_ok) {
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ok = b.CreateAnd(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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}
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// Handle unconditional branches without extra fluff.
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BasicBlock* original_bb = b.GetInsertBlock();
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if (ok) {
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char name[32];
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xesnprintfa(name, XECOUNT(name), "loc_%.8X_bcx", i.address);
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BasicBlock* next_block = g.GetNextBasicBlock();
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BasicBlock* branch_bb = BasicBlock::Create(*g.context(), name, g.gen_fn(),
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next_block);
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b.CreateCondBr(ok, branch_bb, next_block);
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b.SetInsertPoint(branch_bb);
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}
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// Note that this occurs entirely within the branch true block.
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uint32_t nia;
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if (i.B.AA) {
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nia = XEEXTS26(i.B.BD << 2);
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} else {
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nia = i.address + XEEXTS26(i.B.BD << 2);
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}
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if (XeEmitBranchTo(g, b, "bcx", i.address, i.B.LK)) {
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return 1;
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}
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b.SetInsertPoint(original_bb);
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return 0;
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}
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XEDISASMR(bcctrx, 0x4C000420, XL )(InstrData& i, InstrDisasm& d) {
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// TODO(benvanik): mnemonics
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d.Init("bcctr", "Branch Conditional to Count Register",
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i.XL.LK ? InstrDisasm::kLR : 0);
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if (!XESELECTBITS(i.XL.BO, 4, 4)) {
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d.AddCR(i.XL.BI >> 2, InstrRegister::kRead);
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}
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d.AddUImmOperand(i.XL.BO, 1);
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d.AddUImmOperand(i.XL.BI, 1);
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d.AddCTR(InstrRegister::kRead);
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return d.Finish();
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}
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XEEMITTER(bcctrx, 0x4C000420, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if cond_ok then
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// NIA <- CTR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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g.update_lr_value(b.getInt32(i.address + 4));
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}
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Value* cond_ok = NULL;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = g.cr_value(i.XL.BI >> 2);
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cr = b.CreateAnd(cr, 1 << (i.XL.BI & 3));
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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cond_ok = b.CreateICmpNE(cr, b.getInt64(0));
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} else {
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cond_ok = b.CreateICmpEQ(cr, b.getInt64(0));
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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if (cond_ok) {
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ok = cond_ok;
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}
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// Handle unconditional branches without extra fluff.
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BasicBlock* original_bb = b.GetInsertBlock();
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if (ok) {
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char name[32];
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xesnprintfa(name, XECOUNT(name), "loc_%.8X_bcctrx", i.address);
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BasicBlock* next_block = g.GetNextBasicBlock();
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XEASSERTNOTNULL(next_block);
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BasicBlock* branch_bb = BasicBlock::Create(*g.context(), name, g.gen_fn(),
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next_block);
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b.CreateCondBr(ok, branch_bb, next_block);
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b.SetInsertPoint(branch_bb);
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}
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// Note that this occurs entirely within the branch true block.
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if (XeEmitBranchTo(g, b, "bcctrx", i.address, i.XL.LK)) {
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return 1;
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}
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b.SetInsertPoint(original_bb);
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return 0;
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}
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XEDISASMR(bclrx, 0x4C000020, XL )(InstrData& i, InstrDisasm& d) {
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std::string name = "bclr";
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if (i.code == 0x4E800020) {
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name = "blr";
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}
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d.Init(name, "Branch Conditional to Link Register",
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i.XL.LK ? InstrDisasm::kLR : 0);
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if (!XESELECTBITS(i.B.BO, 2, 2)) {
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d.AddCTR(InstrRegister::kReadWrite);
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}
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if (!XESELECTBITS(i.B.BO, 4, 4)) {
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d.AddCR(i.B.BI >> 2, InstrRegister::kRead);
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}
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d.AddUImmOperand(i.XL.BO, 1);
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d.AddUImmOperand(i.XL.BI, 1);
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d.AddLR(InstrRegister::kRead);
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return d.Finish();
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}
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XEEMITTER(bclrx, 0x4C000020, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3]
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// NIA <- LR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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g.update_lr_value(b.getInt32(i.address + 4));
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}
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Value* ctr_ok = NULL;
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if (XESELECTBITS(i.XL.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = g.ctr_value();
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ctr = b.CreateSub(ctr, b.getInt64(1));
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// Ctr check.
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if (XESELECTBITS(i.XL.BO, 1, 1)) {
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ctr_ok = b.CreateICmpEQ(ctr, b.getInt64(0));
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} else {
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ctr_ok = b.CreateICmpNE(ctr, b.getInt64(0));
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}
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}
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Value* cond_ok = NULL;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = g.cr_value(i.XL.BI >> 2);
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cr = b.CreateAnd(cr, 1 << (i.XL.BI & 3));
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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cond_ok = b.CreateICmpNE(cr, b.getInt64(0));
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} else {
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cond_ok = b.CreateICmpEQ(cr, b.getInt64(0));
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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if (ctr_ok && cond_ok) {
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ok = b.CreateAnd(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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}
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// Handle unconditional branches without extra fluff.
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BasicBlock* original_bb = b.GetInsertBlock();
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if (ok) {
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char name[32];
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xesnprintfa(name, XECOUNT(name), "loc_%.8X_bclrx", i.address);
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BasicBlock* next_block = g.GetNextBasicBlock();
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XEASSERTNOTNULL(next_block);
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BasicBlock* branch_bb = BasicBlock::Create(*g.context(), name, g.gen_fn(),
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next_block);
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b.CreateCondBr(ok, branch_bb, next_block);
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b.SetInsertPoint(branch_bb);
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}
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// Note that this occurs entirely within the branch true block.
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if (XeEmitBranchTo(g, b, "bclrx", i.address, i.XL.LK)) {
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return 1;
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}
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b.SetInsertPoint(original_bb);
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return 0;
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}
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// Condition register logical (A-23)
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XEEMITTER(crand, 0x4C000202, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crandc, 0x4C000102, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(creqv, 0x4C000242, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnand, 0x4C0001C2, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnor, 0x4C000042, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(cror, 0x4C000382, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(crorc, 0x4C000342, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(crxor, 0x4C000182, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(mcrf, 0x4C000000, XL )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
|
|
// System linkage (A-24)
|
|
|
|
XEEMITTER(sc, 0x44000002, SC )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
|
|
// Trap (A-25)
|
|
|
|
int XeEmitTrap(FunctionGenerator& g, IRBuilder<>& b, InstrData& i,
|
|
Value* va, Value* vb, uint32_t TO) {
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
// Bits swapped:
|
|
// 01234
|
|
// 43210
|
|
|
|
if (!TO) {
|
|
return 0;
|
|
}
|
|
|
|
BasicBlock* after_bb = BasicBlock::Create(*g.context(), "", g.gen_fn(),
|
|
g.GetNextBasicBlock());
|
|
BasicBlock* trap_bb = BasicBlock::Create(*g.context(), "", g.gen_fn(),
|
|
after_bb);
|
|
|
|
// Create the basic blocks (so we can chain).
|
|
std::vector<BasicBlock*> bbs;
|
|
if (TO & (1 << 4)) {
|
|
bbs.push_back(BasicBlock::Create(*g.context(), "", g.gen_fn(), trap_bb));
|
|
}
|
|
if (TO & (1 << 3)) {
|
|
bbs.push_back(BasicBlock::Create(*g.context(), "", g.gen_fn(), trap_bb));
|
|
}
|
|
if (TO & (1 << 2)) {
|
|
bbs.push_back(BasicBlock::Create(*g.context(), "", g.gen_fn(), trap_bb));
|
|
}
|
|
if (TO & (1 << 1)) {
|
|
bbs.push_back(BasicBlock::Create(*g.context(), "", g.gen_fn(), trap_bb));
|
|
}
|
|
if (TO & (1 << 0)) {
|
|
bbs.push_back(BasicBlock::Create(*g.context(), "", g.gen_fn(), trap_bb));
|
|
}
|
|
bbs.push_back(after_bb);
|
|
|
|
// Jump to the first bb.
|
|
b.CreateBr(bbs.front());
|
|
|
|
// Setup each basic block.
|
|
std::vector<BasicBlock*>::iterator it = bbs.begin();
|
|
if (TO & (1 << 4)) {
|
|
// a < b
|
|
BasicBlock* bb = *(it++);
|
|
b.SetInsertPoint(bb);
|
|
Value* cmp = b.CreateICmpSLT(va, vb);
|
|
b.CreateCondBr(cmp, trap_bb, *it);
|
|
}
|
|
if (TO & (1 << 3)) {
|
|
// a > b
|
|
BasicBlock* bb = *(it++);
|
|
b.SetInsertPoint(bb);
|
|
Value* cmp = b.CreateICmpSGT(va, vb);
|
|
b.CreateCondBr(cmp, trap_bb, *it);
|
|
}
|
|
if (TO & (1 << 2)) {
|
|
// a = b
|
|
BasicBlock* bb = *(it++);
|
|
b.SetInsertPoint(bb);
|
|
Value* cmp = b.CreateICmpEQ(va, vb);
|
|
b.CreateCondBr(cmp, trap_bb, *it);
|
|
}
|
|
if (TO & (1 << 1)) {
|
|
// a <u b
|
|
BasicBlock* bb = *(it++);
|
|
b.SetInsertPoint(bb);
|
|
Value* cmp = b.CreateICmpULT(va, vb);
|
|
b.CreateCondBr(cmp, trap_bb, *it);
|
|
}
|
|
if (TO & (1 << 0)) {
|
|
// a >u b
|
|
BasicBlock* bb = *(it++);
|
|
b.SetInsertPoint(bb);
|
|
Value* cmp = b.CreateICmpUGT(va, vb);
|
|
b.CreateCondBr(cmp, trap_bb, *it);
|
|
}
|
|
|
|
// Create trap BB.
|
|
b.SetInsertPoint(trap_bb);
|
|
g.SpillRegisters();
|
|
// TODO(benvanik): use @llvm.debugtrap? could make debugging better
|
|
b.CreateCall2(g.gen_module()->getFunction("XeTrap"),
|
|
g.gen_fn()->arg_begin(),
|
|
b.getInt32(i.address));
|
|
b.CreateBr(after_bb);
|
|
|
|
// Resume.
|
|
b.SetInsertPoint(after_bb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
XEDISASMR(td, 0x7C000088, X )(InstrData& i, InstrDisasm& d) {
|
|
d.Init("td", "Trap Doubleword", 0);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.X.RA, InstrRegister::kRead);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.X.RB, InstrRegister::kRead);
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(td, 0x7C000088, X )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// a <- (RA)
|
|
// b <- (RB)
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
return XeEmitTrap(g, b, i,
|
|
g.gpr_value(i.X.RA),
|
|
g.gpr_value(i.X.RB),
|
|
i.X.RT);
|
|
}
|
|
|
|
XEDISASMR(tdi, 0x08000000, D )(InstrData& i, InstrDisasm& d) {
|
|
d.Init("tdi", "Trap Doubleword Immediate", 0);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.D.RA, InstrRegister::kRead);
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(tdi, 0x08000000, D )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// a <- (RA)
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
return XeEmitTrap(g, b, i,
|
|
g.gpr_value(i.D.RA),
|
|
b.getInt64(XEEXTS16(i.D.DS)),
|
|
i.D.RT);
|
|
}
|
|
|
|
XEDISASMR(tw, 0x7C000008, X )(InstrData& i, InstrDisasm& d) {
|
|
d.Init("tw", "Trap Word", 0);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.X.RA, InstrRegister::kRead);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.X.RB, InstrRegister::kRead);
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(tw, 0x7C000008, X )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// b <- EXTS((RB)[32:63])
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
return XeEmitTrap(g, b, i,
|
|
b.CreateSExt(b.CreateTrunc(g.gpr_value(i.X.RA),
|
|
b.getInt32Ty()),
|
|
b.getInt64Ty()),
|
|
b.CreateSExt(b.CreateTrunc(g.gpr_value(i.X.RB),
|
|
b.getInt32Ty()),
|
|
b.getInt64Ty()),
|
|
i.X.RT);
|
|
}
|
|
|
|
XEDISASMR(twi, 0x0C000000, D )(InstrData& i, InstrDisasm& d) {
|
|
d.Init("twi", "Trap Word Immediate", 0);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.D.RA, InstrRegister::kRead);
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(twi, 0x0C000000, D )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
return XeEmitTrap(g, b, i,
|
|
b.CreateSExt(b.CreateTrunc(g.gpr_value(i.D.RA),
|
|
b.getInt32Ty()),
|
|
b.getInt64Ty()),
|
|
b.getInt64(XEEXTS16(i.D.DS)),
|
|
i.D.RT);
|
|
}
|
|
|
|
|
|
// Processor control (A-26)
|
|
|
|
XEEMITTER(mfcr, 0x7C000026, X )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEDISASMR(mfspr, 0x7C0002A6, XFX)(InstrData& i, InstrDisasm& d) {
|
|
d.Init("mfspr", "Move From Special Purpose Register", 0);
|
|
d.AddRegOperand(InstrRegister::kGPR, i.XFX.RT, InstrRegister::kWrite);
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
d.AddRegOperand(InstrRegister::kXER, 0, InstrRegister::kRead);
|
|
break;
|
|
case 8:
|
|
d.AddRegOperand(InstrRegister::kLR, 0, InstrRegister::kRead);
|
|
break;
|
|
case 9:
|
|
d.AddRegOperand(InstrRegister::kCTR, 0, InstrRegister::kRead);
|
|
break;
|
|
}
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(mfspr, 0x7C0002A6, XFX)(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// RT <- SPR(n)
|
|
// else
|
|
// RT <- i32.0 || SPR(n)
|
|
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
Value* v = NULL;
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
v = g.xer_value();
|
|
break;
|
|
case 8:
|
|
// LR
|
|
v = g.lr_value();
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
v = g.ctr_value();
|
|
break;
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
g.update_gpr_value(i.XFX.RT, v);
|
|
|
|
return 0;
|
|
}
|
|
|
|
XEEMITTER(mftb, 0x7C0002E6, XFX)(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(mtcrf, 0x7C000120, XFX)(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEDISASMR(mtspr, 0x7C0003A6, XFX)(InstrData& i, InstrDisasm& d) {
|
|
d.Init("mtspr", "Move To Special Purpose Register", 0);
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
d.AddRegOperand(InstrRegister::kXER, 0, InstrRegister::kWrite);
|
|
break;
|
|
case 8:
|
|
d.AddRegOperand(InstrRegister::kLR, 0, InstrRegister::kWrite);
|
|
break;
|
|
case 9:
|
|
d.AddRegOperand(InstrRegister::kCTR, 0, InstrRegister::kWrite);
|
|
break;
|
|
}
|
|
d.AddRegOperand(InstrRegister::kGPR, i.XFX.RT, InstrRegister::kRead);
|
|
return d.Finish();
|
|
}
|
|
XEEMITTER(mtspr, 0x7C0003A6, XFX)(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// SPR(n) <- (RS)
|
|
// else
|
|
// SPR(n) <- (RS)[32:63]
|
|
|
|
Value* v = g.gpr_value(i.XFX.RT);
|
|
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
g.update_xer_value(v);
|
|
break;
|
|
case 8:
|
|
// LR
|
|
g.update_lr_value(v);
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
g.update_ctr_value(v);
|
|
break;
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void RegisterEmitCategoryControl() {
|
|
XEREGISTERINSTR(bx, 0x48000000);
|
|
XEREGISTERINSTR(bcx, 0x40000000);
|
|
XEREGISTERINSTR(bcctrx, 0x4C000420);
|
|
XEREGISTERINSTR(bclrx, 0x4C000020);
|
|
XEREGISTEREMITTER(crand, 0x4C000202);
|
|
XEREGISTEREMITTER(crandc, 0x4C000102);
|
|
XEREGISTEREMITTER(creqv, 0x4C000242);
|
|
XEREGISTEREMITTER(crnand, 0x4C0001C2);
|
|
XEREGISTEREMITTER(crnor, 0x4C000042);
|
|
XEREGISTEREMITTER(cror, 0x4C000382);
|
|
XEREGISTEREMITTER(crorc, 0x4C000342);
|
|
XEREGISTEREMITTER(crxor, 0x4C000182);
|
|
XEREGISTEREMITTER(mcrf, 0x4C000000);
|
|
XEREGISTEREMITTER(sc, 0x44000002);
|
|
XEREGISTERINSTR(td, 0x7C000088);
|
|
XEREGISTERINSTR(tdi, 0x08000000);
|
|
XEREGISTERINSTR(tw, 0x7C000008);
|
|
XEREGISTERINSTR(twi, 0x0C000000);
|
|
XEREGISTEREMITTER(mfcr, 0x7C000026);
|
|
XEREGISTERINSTR(mfspr, 0x7C0002A6);
|
|
XEREGISTEREMITTER(mftb, 0x7C0002E6);
|
|
XEREGISTEREMITTER(mtcrf, 0x7C000120);
|
|
XEREGISTERINSTR(mtspr, 0x7C0003A6);
|
|
}
|
|
|
|
|
|
} // namespace codegen
|
|
} // namespace cpu
|
|
} // namespace xe
|