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61 commits

Author SHA1 Message Date
Triang3l 9a4643d0f2 [GPU] Non-ROV f24 trunc/round, host shader modifications, cache dir 2020-12-07 22:31:46 +03:00
Joel Linn f6dc9ad517 [GPU] Skip viz-query geometry (if marked). 
Document research about viz queries.

v2: Remove viz status unions and move comments to register definitions.
    Add contributors to TODOs.

v3: Comment out unused variables.
    Add TODO for correctly dropping draw calls with memexport.
    Register comment formatting.
 2020-11-21 21:55:52 +03:00
Sandy Carter 382dd8860f [threading] Change thread names to suit pthread 
Shorten names to 16.
Rename Win32 to Windowing.
Shorten GraphicsSystem thread names due to 16 length limit of pthread.
Without this change, both show up as GraphicsSystem.
Remove redundant "Worker" and "Thread" from names.
Remove redundant thread handle from thread name.
 2020-11-15 11:12:05 -06:00
Gliniak 87a3c5fac2 [GPU] Added Stub for Packet: PM4_WAIT_FOR_IDLE 2020-11-10 22:48:00 +03:00
Triang3l 81bc33523a [GPU] Remove unused FinalizeTrace 2020-10-08 21:37:29 +03:00
Triang3l b84239d507 [GPU] xenos.h: max texture size, interpolators 2020-07-11 18:56:56 +03:00
Triang3l 4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Joel Linn 68dd818029 [GPU] Add workaround for occlusion queries. 2020-06-01 22:40:55 -05:00
Triang3l 4631b2b16c [D3D12] Apply half pixel offset through viewport, remove some 2560 references 2020-05-11 20:37:02 +03:00
gibbed ed04d96e67 Avoid using '#' format spec for X hex numbers. 
Avoid using '#' format spec for X (uppercase) hex numbers, as it
results in output like "0XABCDEF" instead of "0xABCDEF".
 2020-04-09 11:25:08 -05:00
gibbed a48bb71c2f Overhaul logging. 2020-04-07 16:09:41 -05:00
gibbed 5bf0b34445 C++17ification. 
C++17ification!

- Filesystem interaction now uses std::filesystem::path.
- Usage of const char*, std::string have been changed to
  std::string_view where appropriate.
- Usage of printf-style functions changed to use fmt.
 2020-04-07 16:09:41 -05:00
Triang3l cde092ece1 [D3D12] Persistent shader and PSO storage 2020-03-21 19:22:19 +03:00
Triang3l 90b772a330 [GPU] Set VGT_DRAW_INITIATOR and use major mode from it 2020-02-24 23:27:25 +03:00
Triang3l c43ccc073d [D3D12] Submit command lists on primary buffer end 2019-12-04 21:42:26 +03:00
Triang3l 4623b41023 [D3D12] Trace guest memory operations 2019-10-23 23:33:50 +03:00
Triang3l a9ed73bdd1 [GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code 2019-10-20 19:40:37 +03:00
Triang3l f83269cf8c [GPU] Refactor: Register structs in D3D12CommandProcessor and some other places 2019-10-19 23:32:38 +03:00
Jonathan Goyvaerts c1af632562 Replace all gflag implementations with cvar implementations 2019-08-03 02:34:07 +02:00
Maksim Derbasov 142148e594 [GPU] Fix bit check in Make Coherent logging. 2019-03-02 04:13:03 -06:00
Margen67 896ac4a682 Update documentation. 
- Convert http to https, provide archive link when possible.
- Made CPU-JIT.png more readable on dark themes;
Added a white background so there isn't black text on a black
background.
 2018-11-22 09:20:09 -06:00
Triang3l 2b03a9e095 [GPU] Synchronize GPU frontend with the D3D12 branch 2018-10-22 23:28:52 +03:00
gibbed ec3ab0adbd [GPU] Stub out context update GPU opcode. 
[Vulkan] Gracefully handle vertex upload failures.
 2018-05-30 20:49:30 -05:00
gibbed 8a099925f3 Shut Travis up. 2018-05-30 10:09:19 -05:00
DrChat f518ec1b37 [GPU] Add coherency debug logs 2018-05-29 19:42:59 -05:00
gibbed ee5724f5dd [GPU] Move gamma ramp tracking to CommandProcessor. 2018-05-22 05:36:24 -05:00
Dr. Chat 87bfad1f74 [GPU] PM4_EVENT_WRITE_EXT destination is /not/ aligned (to 16 bytes) 2018-04-29 18:26:36 -05:00
DrChat 1d4fa80eac [GPU] Fixup ringbuffer log2_size (which specifies size in qwords) 
Save microengine init packets
 2018-04-08 15:50:36 -05:00
DrChat ffef59aaa5 [Base] RingBuffer: Add ReadAndSwap instead of piggybacking off of Read 2018-02-18 12:18:20 -06:00
Dr. Chat 3d1c2a6c9a [GPU] Update vizquery documentation 2018-02-16 22:03:33 -06:00
DrChat 29c5fb8022 [GPU] Short circuit command processor waits if an exit is requested. 2017-12-18 17:23:14 -06:00
DrChat b5d647d540 [Vulkan] Better handling of device lost events (present fatal error dialog) 2017-12-18 14:27:00 -06:00
DrChat d4338a2c3f [GPU] Use overall shorter names for xenia GPU traces 2017-12-17 15:00:10 -06:00
DrChat 8cabc114e9 [GPU] Properly track the packets leading up to a swap command 2017-12-15 22:01:50 -06:00
Cesys 8c4ca35a35 Ringbuffer init fix 2017-03-25 20:00:48 -07:00
Vlad Ivanov f0ba717142 Fix a bunch of missing cmath includes 
...as well as missing std:: namespace specifiers
 2017-02-07 20:26:08 +03:00
Dr. Chat d9b52d1afa GPU: Add a "low-power" state. 2017-01-28 20:59:41 -06:00
Dr. Chat 26d81abf52 IssueDraw failing in the backend does not mean we need to stop processing commands 2016-10-21 18:14:24 -05:00
Dr. Chat 212cd6ee3d GPU: Log a warning on writes to unknown registers. 2016-06-25 10:32:48 -05:00
Dr. Chat 27c16b1936 GPU: Fix incorrectly calculating the primary ringbuffer's size 2016-06-16 21:30:06 -05:00
Ben Vanik cd02cdfc70 Making memory API less error prone; fixes buffer/constant uploads. 2016-02-20 19:19:29 -08:00
Dr. Chat a2dd1c48ae Add some WIP viz query notes to the command processor. 
Also implement PM4_SET_BIN_MASK/SELECT.
 2016-02-16 18:36:43 -06:00
Dr. Chat 4335e41c14 Decouple MicroProfileFlip from Profiler::Present (and start a new frame in XE_SWAP) 2016-02-07 19:25:30 -06:00
Dr. Chat 6ce28ffd8c Command Processor: Replace RingbufferReader with RingBuffer 
Report any packet processing errors
PM4_MEM_WRITE
 2016-01-24 22:54:26 -06:00
Ben Vanik f26bea88d9 Replacing zlib with snappy in traces, adding trace header, docs. 2015-12-30 22:58:22 -08:00
Dr. Chat 6997970d52 GraphicsSystem Save/Restore 2015-12-29 13:09:41 -08:00
Ben Vanik 522ff9d23e Alternate indirect buffer command. 2015-12-07 19:16:01 -08:00
Ben Vanik bea8870700 Shuffling old-style ucode.h under gl4. 2015-11-28 16:10:27 -08:00
Ben Vanik b750875e9d Fixing style. 2015-11-21 19:07:07 -08:00
Robert Dupuis bdec7a063f Implemented REG_TO_MEM GPU opcode 2015-11-21 21:20:34 -05:00