From 9c8e0cc53eb7b1a241d86f7e9d573cecd6a2cc16 Mon Sep 17 00:00:00 2001 From: Triang3l Date: Thu, 5 May 2022 13:13:30 +0300 Subject: [PATCH] [GPU] DC_LUT_PWL_DATA comment fix [ci skip] --- src/xenia/gpu/command_processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/xenia/gpu/command_processor.cc b/src/xenia/gpu/command_processor.cc index e6422bc73..f935f22ec 100644 --- a/src/xenia/gpu/command_processor.cc +++ b/src/xenia/gpu/command_processor.cc @@ -405,7 +405,7 @@ void CommandProcessor::WriteRegister(uint32_t index, uint32_t value) { auto& gamma_ramp_rw_index = regs.Get(); // Bit 7 of the index is ignored for PWL. uint32_t gamma_ramp_rw_index_pwl = gamma_ramp_rw_index.rw_index & 0x7F; - // DC_LUT_RW_INDEX is likely in the red, green, blue order because + // DC_LUT_PWL_DATA is likely in the red, green, blue order because // DC_LUT_SEQ_COLOR is, but the write enable mask is blue, green, red. bool write_gamma_ramp_component = (regs[XE_GPU_REG_DC_LUT_WRITE_EN_MASK].u32 &