From 83ff0c501bb4b73165c511e5f0a02396bb5cee62 Mon Sep 17 00:00:00 2001
From: "Herman S." <429230+has207@users.noreply.github.com>
Date: Sun, 19 Oct 2025 13:38:54 +0900
Subject: [PATCH] [CPU] Set VSCR NJ (non-Java) bit

---
 src/xenia/cpu/thread_state.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/xenia/cpu/thread_state.cc b/src/xenia/cpu/thread_state.cc
index 42b8a3f0a..bc1315887 100644
--- a/src/xenia/cpu/thread_state.cc
+++ b/src/xenia/cpu/thread_state.cc
@@ -93,7 +93,9 @@ ThreadState::ThreadState(Processor* processor, uint32_t thread_id,
   // Set initial registers.
   context_->r[1] = stack_base;
   context_->r[13] = pcr_address;
-  // fixme: VSCR must be set here!
+  // VSCR - Vector Status and Control Register
+  // NJ bit (bit 16) = 1: Non-Java IEEE mode (default for Xbox 360)
+  context_->vscr_vec = vec128i(0, 0, 0, 0x00010000);
   context_->msr = 0x9030;  // dumped from a real 360, 0x8000
 
   // this register can be used for arbitrary data according to the PPC docs