diff --git a/src/xenia/cpu/testing/vector_sha_test.cc b/src/xenia/cpu/testing/vector_sha_test.cc
index 5b4adabc6..187e8b4f2 100644
--- a/src/xenia/cpu/testing/vector_sha_test.cc
+++ b/src/xenia/cpu/testing/vector_sha_test.cc
@@ -58,6 +58,28 @@ TEST_CASE("VECTOR_SHA_I8_CONSTANT", "[instr]") {
       });
 }
 
+// This targets the "all_same" optimization of the Int8 specialization of
+// VECTOR_SHA_V128
+TEST_CASE("VECTOR_SHA_I8_SAME_CONSTANT", "[instr]") {
+  TestFunction test([](HIRBuilder& b) {
+    StoreVR(
+        b, 3,
+        b.VectorSha(LoadVR(b, 4), b.LoadConstantVec128(vec128b(5)), INT8_TYPE));
+    b.Return();
+  });
+  test.Run(
+      [](PPCContext* ctx) {
+        ctx->v[4] = vec128b(0x7E, 0x7E, 0x7E, 0x7F, 0x80, 0xFF, 0x01, 0x12,
+                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+      },
+      [](PPCContext* ctx) {
+        auto result = ctx->v[3];
+        REQUIRE(result == vec128b(0x03, 0x03, 0x03, 0x03, 0xfc, 0xff, 0x00,
+                                  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                  0x00, 0x00));
+      });
+}
+
 TEST_CASE("VECTOR_SHA_I16", "[instr]") {
   TestFunction test([](HIRBuilder& b) {
     StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE));