From 8c4ca35a350403cd14cbd1cb453e581137d5d9fb Mon Sep 17 00:00:00 2001 From: Cesys Date: Sat, 25 Mar 2017 20:00:48 -0700 Subject: [PATCH] Ringbuffer init fix --- src/xenia/gpu/command_processor.cc | 1 + src/xenia/gpu/vulkan/pipeline_cache.cc | 1 + 2 files changed, 2 insertions(+) diff --git a/src/xenia/gpu/command_processor.cc b/src/xenia/gpu/command_processor.cc index 73f79923b..6ab30e22e 100644 --- a/src/xenia/gpu/command_processor.cc +++ b/src/xenia/gpu/command_processor.cc @@ -229,6 +229,7 @@ bool CommandProcessor::SetupContext() { return true; } void CommandProcessor::ShutdownContext() { context_.reset(); } void CommandProcessor::InitializeRingBuffer(uint32_t ptr, uint32_t log2_size) { + read_ptr_index_ = 0; primary_buffer_ptr_ = ptr; primary_buffer_size_ = uint32_t(std::pow(2u, log2_size)); } diff --git a/src/xenia/gpu/vulkan/pipeline_cache.cc b/src/xenia/gpu/vulkan/pipeline_cache.cc index 69cf3d8b4..f402b02ba 100644 --- a/src/xenia/gpu/vulkan/pipeline_cache.cc +++ b/src/xenia/gpu/vulkan/pipeline_cache.cc @@ -1074,6 +1074,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateInputAssemblyState( } // TODO(benvanik): no way to specify in Vulkan? assert_true(regs.multi_prim_ib_reset_index == 0xFFFF || + regs.multi_prim_ib_reset_index == 0xFFFFFF || regs.multi_prim_ib_reset_index == 0xFFFFFFFF); // glPrimitiveRestartIndex(regs.multi_prim_ib_reset_index);