From 3a90f7a24627f6f8add15d10101a7610433d8081 Mon Sep 17 00:00:00 2001
From: Triang3l <triang3l@yandex.ru>
Date: Tue, 24 Jul 2018 16:47:55 +0300
Subject: [PATCH] [D3D12] Enable instruction numbers and offsets in DXBC
 disassembly

---
 src/xenia/gpu/d3d12/d3d12_shader.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/xenia/gpu/d3d12/d3d12_shader.cc b/src/xenia/gpu/d3d12/d3d12_shader.cc
index dd5407934..8dc86bc1c 100644
--- a/src/xenia/gpu/d3d12/d3d12_shader.cc
+++ b/src/xenia/gpu/d3d12/d3d12_shader.cc
@@ -89,7 +89,9 @@ bool D3D12Shader::Prepare() {
   if (FLAGS_d3d12_shader_disasm) {
     ID3DBlob* disassembly_blob;
     if (SUCCEEDED(D3DDisassemble(blob_->GetBufferPointer(),
-                                 blob_->GetBufferSize(), 0, nullptr,
+                                 blob_->GetBufferSize(),
+                                 D3D_DISASM_ENABLE_INSTRUCTION_NUMBERING |
+                                 D3D_DISASM_ENABLE_INSTRUCTION_OFFSET, nullptr,
                                  &disassembly_blob))) {
       host_disassembly_ =
           reinterpret_cast<const char*>(disassembly_blob->GetBufferPointer());