diff --git a/src/xenia/gpu/command_processor.cc b/src/xenia/gpu/command_processor.cc
index d957f432c..960cc8294 100644
--- a/src/xenia/gpu/command_processor.cc
+++ b/src/xenia/gpu/command_processor.cc
@@ -236,7 +236,7 @@ void CommandProcessor::ShutdownContext() { context_.reset(); }
 void CommandProcessor::InitializeRingBuffer(uint32_t ptr, uint32_t log2_size) {
   read_ptr_index_ = 0;
   primary_buffer_ptr_ = ptr;
-  primary_buffer_size_ = uint32_t(std::pow(2u, log2_size));
+  primary_buffer_size_ = 1 << log2_size;
 }
 
 void CommandProcessor::EnableReadPointerWriteBack(uint32_t ptr,
@@ -695,7 +695,11 @@ bool CommandProcessor::ExecutePacketType3_ME_INIT(RingBuffer* reader,
                                                   uint32_t packet,
                                                   uint32_t count) {
   // initialize CP's micro-engine
-  reader->AdvanceRead(count * sizeof(uint32_t));
+  me_bin_.clear();
+  for (uint32_t i = 0; i < count; i++) {
+    me_bin_.push_back(reader->ReadAndSwap<uint32_t>());
+  }
+
   return true;
 }
 
diff --git a/src/xenia/gpu/command_processor.h b/src/xenia/gpu/command_processor.h
index a418dd683..7cfedb0f9 100644
--- a/src/xenia/gpu/command_processor.h
+++ b/src/xenia/gpu/command_processor.h
@@ -215,6 +215,9 @@ class CommandProcessor {
   std::function<void()> swap_request_handler_;
   std::queue<std::function<void()>> pending_fns_;
 
+  // MicroEngine binary from PM4_ME_INIT
+  std::vector<uint32_t> me_bin_;
+
   uint32_t counter_ = 0;
 
   uint32_t primary_buffer_ptr_ = 0;
diff --git a/src/xenia/gpu/graphics_system.cc b/src/xenia/gpu/graphics_system.cc
index 56443db3a..7728e8eee 100644
--- a/src/xenia/gpu/graphics_system.cc
+++ b/src/xenia/gpu/graphics_system.cc
@@ -170,7 +170,7 @@ uint32_t GraphicsSystem::ReadRegister(uint32_t addr) {
   uint32_t r = (addr & 0xFFFF) / 4;
 
   switch (r) {
-    case 0x0F00:  // ?
+    case 0x0F00:  // RB_EDRAM_TIMING
       return 0x08100748;
     case 0x0F01:  // RB_BC_CONTROL
       return 0x0000200E;
@@ -211,7 +211,7 @@ void GraphicsSystem::WriteRegister(uint32_t addr, uint32_t value) {
 }
 
 void GraphicsSystem::InitializeRingBuffer(uint32_t ptr, uint32_t log2_size) {
-  command_processor_->InitializeRingBuffer(ptr, (log2_size | 0x2) + 1);
+  command_processor_->InitializeRingBuffer(ptr, log2_size + 0x3);
 }
 
 void GraphicsSystem::EnableReadPointerWriteBack(uint32_t ptr,
diff --git a/src/xenia/kernel/xboxkrnl/xboxkrnl_video.cc b/src/xenia/kernel/xboxkrnl/xboxkrnl_video.cc
index d2675f125..3491b272d 100644
--- a/src/xenia/kernel/xboxkrnl/xboxkrnl_video.cc
+++ b/src/xenia/kernel/xboxkrnl/xboxkrnl_video.cc
@@ -205,12 +205,6 @@ DECLARE_XBOXKRNL_EXPORT(VdSetGraphicsInterruptCallback, ExportTag::kVideo);
 void VdInitializeRingBuffer(lpvoid_t ptr, int_t log2_size) {
   // r3 = result of MmGetPhysicalAddress
   // r4 = log2(size)
-  // r4 is or'd with 0x802 and then stuffed into CP_RB_CNTL
-  // according to AMD docs, this corresponds with RB_BUFSZ, which is log2
-  // actual size.
-  // 0x8 is RB_BLKSZ, or number of words gpu will read before updating the
-  // host read pointer.
-  // So being or'd with 0x2 makes the ring buffer size always a multiple of 4.
   // Buffer pointers are from MmAllocatePhysicalMemory with WRITE_COMBINE.
   auto graphics_system = kernel_state()->emulator()->graphics_system();
   graphics_system->InitializeRingBuffer(ptr, log2_size);