From 1b3351b1e28f1064de60f6b712cd5c39b1fb1eeb Mon Sep 17 00:00:00 2001 From: Rick Gibbed Date: Sun, 26 May 2013 08:39:31 -0700 Subject: [PATCH] disasm for mfmsr, mtmsr, mtmsrd --- src/xenia/cpu/ppc/disasm_control.cc | 23 +++++++++++++++++++++++ src/xenia/cpu/ppc/instr_tables.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/src/xenia/cpu/ppc/disasm_control.cc b/src/xenia/cpu/ppc/disasm_control.cc index f5f857dd2..6dca6c89f 100644 --- a/src/xenia/cpu/ppc/disasm_control.cc +++ b/src/xenia/cpu/ppc/disasm_control.cc @@ -216,6 +216,26 @@ XEDISASMR(mtspr, 0x7C0003A6, XFX)(InstrData& i, InstrDisasm& d) { return d.Finish(); } +XEDISASMR(mfmsr, 0x7C0000A6, X)(InstrData& i, InstrDisasm& d) { + d.Init("mfmsr", "Move From Machine State Register", 0); + d.AddRegOperand(InstrRegister::kGPR, i.X.RT, InstrRegister::kWrite); + return d.Finish(); +} + +XEDISASMR(mtmsr, 0x7C000124, X)(InstrData& i, InstrDisasm& d) { + d.Init("mtmsr", "Move To Machine State Register", 0); + d.AddRegOperand(InstrRegister::kGPR, i.X.RT, InstrRegister::kRead); + d.AddSImmOperand((i.X.RA & 16 != 0) ? 1 : 0, 1); + return d.Finish(); +} + +XEDISASMR(mtmsrd, 0x7C000164, X)(InstrData& i, InstrDisasm& d) { + d.Init("mtmsrd", "Move To Machine State Register Doubleword", 0); + d.AddRegOperand(InstrRegister::kGPR, i.X.RT, InstrRegister::kRead); + d.AddSImmOperand((i.X.RA & 16 != 0) != 0 ? 1 : 0, 1); + return d.Finish(); +} + void RegisterDisasmCategoryControl() { XEREGISTERINSTR(bx, 0x48000000); @@ -241,6 +261,9 @@ void RegisterDisasmCategoryControl() { XEREGISTERINSTR(mftb, 0x7C0002E6); XEREGISTERINSTR(mtcrf, 0x7C000120); XEREGISTERINSTR(mtspr, 0x7C0003A6); + XEREGISTERINSTR(mfmsr, 0x7C0000A6); + XEREGISTERINSTR(mtmsr, 0x7C000124); + XEREGISTERINSTR(mtmsrd, 0x7C000164); } diff --git a/src/xenia/cpu/ppc/instr_tables.h b/src/xenia/cpu/ppc/instr_tables.h index a976a03fd..f3fc082e1 100644 --- a/src/xenia/cpu/ppc/instr_tables.h +++ b/src/xenia/cpu/ppc/instr_tables.h @@ -115,6 +115,7 @@ static InstrType instr_table_31_unprep[] = { INSTRUCTION(lvewx, 0x7C00008E, X , General , 0), INSTRUCTION(mulhdx, 0x7C000092, XO , General , 0), INSTRUCTION(mulhwx, 0x7C000096, XO , General , 0), + INSTRUCTION(mfmsr, 0x7C0000A6, X , General , 0), INSTRUCTION(ldarx, 0x7C0000A8, X , General , 0), INSTRUCTION(dcbf, 0x7C0000AC, X , General , 0), INSTRUCTION(lbzx, 0x7C0000AE, X , General , 0), @@ -126,10 +127,12 @@ static InstrType instr_table_31_unprep[] = { INSTRUCTION(subfex, 0x7C000110, XO , General , 0), INSTRUCTION(addex, 0x7C000114, XO , General , 0), INSTRUCTION(mtcrf, 0x7C000120, XFX, General , 0), + INSTRUCTION(mtmsr, 0x7C000124, X , General , 0), INSTRUCTION(stdx, 0x7C00012A, X , General , 0), INSTRUCTION(stwcx, 0x7C00012D, X , General , 0), INSTRUCTION(stwx, 0x7C00012E, X , General , 0), INSTRUCTION(stvehx, 0x7C00014E, X , General , 0), + INSTRUCTION(mtmsrd, 0x7C000164, X , General , 0), INSTRUCTION(stdux, 0x7C00016A, X , General , 0), INSTRUCTION(stwux, 0x7C00016E, X , General , 0), INSTRUCTION(stvewx, 0x7C00018E, X , General , 0),