mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
237a329226
Add support direct clock for AIC3204 from si5351 Now possible made calibration and not reset old calibration data, just made another calibration (not need reset or disable correction). Open - Short calibration depend from self, need recalibrate it together. Load calibration possible made alone Isoln, Thru also depend from self, need recalibrate it together.
301 lines
11 KiB
C
301 lines
11 KiB
C
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hal.h"
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#include "nanovna.h"
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#define AIC3204_ADDR 0x18
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#define wait_ms(ms) chThdSleepMilliseconds(ms)
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// Register - 0x01 / 0x34 (P1_R52): Left MICPGA Positive Terminal Input Routing Configuration
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#define REG_34_IN1L_TO_LEFT_P_NO (0<<6)
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#define REG_34_IN1L_TO_LEFT_P_10k (1<<6)
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#define REG_34_IN1L_TO_LEFT_P_20k (2<<6)
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#define REG_34_IN1L_TO_LEFT_P_40k (3<<6)
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#define REG_34_IN2L_TO_LEFT_P_NO (0<<4)
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#define REG_34_IN2L_TO_LEFT_P_10k (1<<4)
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#define REG_34_IN2L_TO_LEFT_P_20k (2<<4)
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#define REG_34_IN2L_TO_LEFT_P_40k (3<<4)
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#define REG_34_IN3L_TO_LEFT_P_NO (0<<2)
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#define REG_34_IN3L_TO_LEFT_P_10k (1<<2)
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#define REG_34_IN3L_TO_LEFT_P_20k (2<<2)
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#define REG_34_IN3L_TO_LEFT_P_40k (3<<2)
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#define REG_34_IN1R_TO_LEFT_P_NO (0<<0)
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#define REG_34_IN1R_TO_LEFT_P_10k (1<<0)
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#define REG_34_IN1R_TO_LEFT_P_20k (2<<0)
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#define REG_34_IN1R_TO_LEFT_P_40k (3<<0)
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// Register - 0x01 / 0x36 (P1_R54): Left MICPGA Negative Terminal Input Routing Configuration
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#define REG_36_CM1L_TO_LEFT_N_NO (0<<6)
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#define REG_36_CM1L_TO_LEFT_N_10k (1<<6)
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#define REG_36_CM1L_TO_LEFT_N_20k (2<<6)
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#define REG_36_CM1L_TO_LEFT_N_40k (3<<6)
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#define REG_36_IN2R_TO_LEFT_N_NO (0<<4)
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#define REG_36_IN2R_TO_LEFT_N_10k (1<<4)
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#define REG_36_IN2R_TO_LEFT_N_20k (2<<4)
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#define REG_36_IN2R_TO_LEFT_N_40k (3<<4)
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#define REG_36_IN3R_TO_LEFT_N_NO (0<<2)
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#define REG_36_IN3R_TO_LEFT_N_10k (1<<2)
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#define REG_36_IN3R_TO_LEFT_N_20k (2<<2)
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#define REG_36_IN3R_TO_LEFT_N_40k (3<<2)
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#define REG_36_CM2L_TO_LEFT_N_NO (0<<0)
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#define REG_36_CM2L_TO_LEFT_N_10k (1<<0)
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#define REG_36_CM2L_TO_LEFT_N_20k (2<<0)
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#define REG_36_CM2L_TO_LEFT_N_40k (3<<0)
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// Register - 0x01 / 0x37 (P1_R55): Right MICPGA Positive Terminal Input Routing Configuration
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#define REG_37_IN1R_TO_RIGHT_P_NO (0<<6)
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#define REG_37_IN1R_TO_RIGHT_P_10k (1<<6)
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#define REG_37_IN1R_TO_RIGHT_P_20k (2<<6)
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#define REG_37_IN1R_TO_RIGHT_P_40k (3<<6)
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#define REG_37_IN2R_TO_RIGHT_P_NO (0<<4)
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#define REG_37_IN2R_TO_RIGHT_P_10k (1<<4)
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#define REG_37_IN2R_TO_RIGHT_P_20k (2<<4)
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#define REG_37_IN2R_TO_RIGHT_P_40k (3<<4)
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#define REG_37_IN3R_TO_RIGHT_P_NO (0<<2)
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#define REG_37_IN3R_TO_RIGHT_P_10k (1<<2)
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#define REG_37_IN3R_TO_RIGHT_P_20k (2<<2)
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#define REG_37_IN3R_TO_RIGHT_P_40k (3<<2)
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#define REG_37_IN2L_TO_RIGHT_P_NO (0<<0)
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#define REG_37_IN2L_TO_RIGHT_P_10k (1<<0)
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#define REG_37_IN2L_TO_RIGHT_P_20k (2<<0)
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#define REG_37_IN2L_TO_RIGHT_P_40k (3<<0)
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// Register - 0x01 / 0x39 (P1_R57): Right MICPGA Negative Terminal Input Routing Configuration
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#define REG_39_CM1R_TO_RIGHT_N_NO (0<<6)
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#define REG_39_CM1R_TO_RIGHT_N_10k (1<<6)
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#define REG_39_CM1R_TO_RIGHT_N_20k (2<<6)
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#define REG_39_CM1R_TO_RIGHT_N_40k (3<<6)
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#define REG_39_IN1L_TO_RIGHT_N_NO (0<<4)
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#define REG_39_IN1L_TO_RIGHT_N_10k (1<<4)
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#define REG_39_IN1L_TO_RIGHT_N_20k (2<<4)
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#define REG_39_IN1L_TO_RIGHT_N_40k (3<<4)
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#define REG_39_IN3L_TO_RIGHT_N_NO (0<<2)
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#define REG_39_IN3L_TO_RIGHT_N_10k (1<<2)
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#define REG_39_IN3L_TO_RIGHT_N_20k (2<<2)
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#define REG_39_IN3L_TO_RIGHT_N_40k (3<<2)
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#define REG_39_CM2R_TO_RIGHT_N_NO (0<<0)
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#define REG_39_CM2R_TO_RIGHT_N_10k (1<<0)
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#define REG_39_CM2R_TO_RIGHT_N_20k (2<<0)
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#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0)
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static const uint8_t conf_data[] = {
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// reg, data, // PLL clock config
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0x00, 0x00, // Initialize to Page 0
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0x01, 0x01, // Initialize the device through software reset
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//=======================================================
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// Configure PLL clock
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// PLL_CLKIN * R * J.D
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// PLL_CLK = ---------------------
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// P
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#if AUDIO_CLOCK_REF == 8000000U
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// MCLK = 8.000MHz * 10.7520 = 86.016MHz,
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0x04, 0x03, // PLL Clock Low (80MHz - 137MHz), MCLK pin is input to PLL, PLL as CODEC_CLKIN
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0x05, 0x91, // Power up PLL, P=1,R=1
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0x06, 0x0a, // J=10
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0x07, 0x1D, // D=7520 = 0x1D60
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0x08, 0x60,
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#elif AUDIO_CLOCK_REF == 10752000U
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// MCLK = 10.752MHz * 4 * 2.0 / 1 = 86.016MHz
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0x04, 0x03, // PLL Clock Low (80MHz - 137MHz),MCLK pin is input to PLL, PLL as CODEC_CLKIN
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0x05, 0x94, // Power up PLL, P=1,R=4
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0x06, 0x02, // J=2
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0x07, 0x00, // D=0
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0x08, 0x00,
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#elif AUDIO_CLOCK_REF == 86016000U
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// MCLK = 86.016MHz
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0x04, 0x00, // MCLK as CODEC_CLKIN
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0x05, 0x00, // Power down PLL
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0x06, 0x00, // J=0
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0x07, 0x00, // D=0
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0x08, 0x00,
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#else
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#error "Need set correct CODEC_CLKIN for aic3204"
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#endif
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// Configure ADC clock
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// CODEC_CLKIN
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// ADC_fs = --------------------
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// NADC * MADC * AOSR
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#if AUDIO_ADC_FREQ == 48000
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// Clock config, default fs=48kHz
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// from PLL 86.016MHz/(2*7*128) = 48kHz
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0x0b, 0x82, // Power up the NDAC divider with value 2
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0x0c, 0x87, // Power up the MDAC divider with value 7
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 128
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0x0e, 0x80, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power down
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0x12, 0x82, // Power up the NADC divider with value 2
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x80, // ADC Oversampling (AOSR) Program the OSR of ADC to 128
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0x3d, 0x01, // Select ADC PRB_R1
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 28,// Enable the BCLKN divider with value 28 (I2S clock = 86.016MHz/(NDAC*28) = 48kHz * (16+16)
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#elif AUDIO_ADC_FREQ == 96000
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// Clock config, default fs=96kHz
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// from PLL 86.016MHz/(2*7*64) = 96kHz
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0x0b, 0x82, // Power up the NDAC divider with value 2
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0x0c, 0x87, // Power up the MDAC divider with value 7
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 64
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0x0e, 0x40, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power up
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0x12, 0x81, // Power up the NADC divider with value 1
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x40, // ADC Oversampling (AOSR) set OSR of ADC to 64
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0x3d, 0x01, // Select ADC PRB_R1 (AOSR = 64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B))
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16)
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#else
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#error "Need set correct ADC clock for aic3204"
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#endif
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// Data routing
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0x00, 0x01, // Select Page 1 */
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0x01, 0x08, // Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
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0x02, 0x01, // Enable Master Analog Power Control
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0x7b, 0x01, // Set the REF charging time to 40ms
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0x14, 0x25, // HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
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0x0a, 0x33, // Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V
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0x3d, 0x00, // Select ADC PTM_R4 */
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// 0x3d, 0xB6, // Select ADC PTM_R2 */
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0x47, 0x32, // Set MicPGA startup delay to 6.4ms
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0x7b, 0x01, // Set the REF charging time to 40ms
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0x34, REG_34_IN2L_TO_LEFT_P_10k, // Route IN2L to LEFT_P with 10K
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0x36, REG_36_IN2R_TO_LEFT_N_10k, // Route IN2R to LEFT_N with 10K
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//0x37, 0x04, // Route IN3R to RIGHT_P with 10K
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//0x39, 0x04, // Route IN3L to RIGHT_N with 10K
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//0x3b, 0x00, // Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB
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//0x3c, 0x00, // Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB
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};
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static const uint8_t conf_data_unmute[] = {
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// reg, data,
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0x00, 0x00, // Select Page 0
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0x51, 0xc2, // Power up Left and Right ADC Channels, ADC Volume Control Soft-Stepping disabled
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0x52, 0x00, // Unmute Left and Right ADC Digital Volume Control
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0x00, 0x01, // Select Page 1 (should be set as default)
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};
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static const uint8_t conf_data_ch3_select[] = {
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// reg, data,
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//0x00, 0x01, // Select Page 1 (should be set as default)
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0x37, REG_37_IN3R_TO_RIGHT_P_10k, // Route IN3R to RIGHT_P with input impedance of 10K
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/*0x38,*/ 0x00, // Reserved
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/*0x39,*/ REG_39_IN3L_TO_RIGHT_N_10k, // Route IN3L to RIGHT_N with input impedance of 10K
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};
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static const uint8_t conf_data_ch1_select[] = {
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// reg, data,
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//0x00, 0x01, // Select Page 1 (should be set as default)
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0x37, REG_37_IN1R_TO_RIGHT_P_10k, // Route IN1R to RIGHT_P with input impedance of 10K
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/*0x38,*/ 0x00, // Reserved
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/*0x39,*/ REG_39_IN1L_TO_RIGHT_N_10k, // Route IN1L to RIGHT_N with input impedance of 10K
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};
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static void
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tlv320aic3204_bulk_write(const uint8_t *buf, int len)
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{
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// i2cAcquireBus(&I2CD1);
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(void)i2cMasterTransmitTimeout(&I2CD1, AIC3204_ADDR, buf, len, NULL, 0, 1000);
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// i2cReleaseBus(&I2CD1);
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}
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#if 0
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static int
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tlv320aic3204_read(uint8_t d0)
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{
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int addr = AIC3204_ADDR;
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uint8_t buf[] = { d0 };
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i2cAcquireBus(&I2CD1);
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i2cMasterTransmitTimeout(&I2CD1, addr, buf, 1, buf, 1, 1000);
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i2cReleaseBus(&I2CD1);
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return buf[0];
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}
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#endif
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static void
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tlv320aic3204_config(const uint8_t *data, int len)
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{
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// i2cAcquireBus(&I2CD1);
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for (; len--; data += 2)
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tlv320aic3204_bulk_write(data, 2);
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// i2cReleaseBus(&I2CD1);
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}
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void tlv320aic3204_init(void)
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{
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tlv320aic3204_config(conf_data, sizeof(conf_data)/2);
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wait_ms(40);
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tlv320aic3204_config(conf_data_unmute, sizeof(conf_data_unmute)/2);
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}
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void
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tlv320aic3204_write_reg(uint8_t page, uint8_t reg, uint8_t data)
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{
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uint8_t buf[] = {
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0x00, page, // Select Page
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reg, data, // write reg data
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0x00, 0x01 // Select Page 1 (should be set as default)
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};
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tlv320aic3204_config(buf, sizeof(buf)/2);
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}
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void tlv320aic3204_select(uint8_t channel)
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{
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// Cache current selected channel
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static uint8_t current_channel = -1;
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if (current_channel == channel)
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return;
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current_channel = channel;
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tlv320aic3204_bulk_write(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch1_select));
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// tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2);
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}
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void tlv320aic3204_set_gain(uint8_t lgain, uint8_t rgain)
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{
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uint8_t data[] = {
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// 0x00, 0x01, // Select Page 1 (should be set as default)
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0x3b, lgain, // Unmute Left MICPGA, set gain
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/*0x3c,*/ rgain // Unmute Right MICPGA, set gain
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};
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// tlv320aic3204_config(data, sizeof(data)/2);
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tlv320aic3204_bulk_write(data, sizeof(data));
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}
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