mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
139 lines
3.3 KiB
C
139 lines
3.3 KiB
C
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "ch.h"
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#include "hal.h"
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#include "nanovna.h"
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#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \
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(uint32_t)(low))
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#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */
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#define ADC_CFGR1_RES_12BIT (0U << 3U)
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void adc_init(void)
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{
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rccEnableADC1(FALSE);
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/* Ensure flag states */
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ADC1->IER = 0;
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/* Calibration procedure.*/
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ADC->CCR = 0;
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if (ADC1->CR & ADC_CR_ADEN) {
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ADC1->CR |= ~ADC_CR_ADDIS; /* Disable ADC */
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}
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while (ADC1->CR & ADC_CR_ADEN)
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;
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ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN;
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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if (ADC1->ISR & ADC_ISR_ADRDY) {
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ADC1->ISR |= ADC_ISR_ADRDY; /* clear ADRDY */
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}
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/* Enable ADC */
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ADC1->CR |= ADC_CR_ADEN;
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while (!(ADC1->ISR & ADC_ISR_ADRDY))
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;
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}
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uint16_t adc_single_read(ADC_TypeDef *adc, uint32_t chsel)
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{
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/* ADC setup */
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adc->ISR = adc->ISR;
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adc->IER = 0;
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adc->TR = ADC_TR(0, 0);
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adc->SMPR = ADC_SMPR_SMP_1P5;
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adc->CFGR1 = ADC_CFGR1_RES_12BIT;
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adc->CHSELR = chsel;
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/* ADC conversion start.*/
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adc->CR |= ADC_CR_ADSTART;
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while (adc->CR & ADC_CR_ADSTART)
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;
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return adc->DR;
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}
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void adc_start_analog_watchdogd(ADC_TypeDef *adc, uint32_t chsel)
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{
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uint32_t cfgr1;
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cfgr1 = ADC_CFGR1_RES_12BIT | ADC_CFGR1_AWDEN
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| ADC_CFGR1_EXTEN_0 // rising edge of external trigger
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| ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1; // TRG3 , /* CFGR1 */
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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adc->ISR = adc->ISR;
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adc->IER = ADC_IER_AWDIE;
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adc->TR = ADC_TR(0, TOUCH_THRESHOLD);
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adc->SMPR = ADC_SMPR_SMP_1P5;
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adc->CHSELR = chsel;
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/* ADC configuration and start.*/
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adc->CFGR1 = cfgr1;
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/* ADC conversion start.*/
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adc->CR |= ADC_CR_ADSTART;
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}
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void adc_stop(ADC_TypeDef *adc)
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{
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if (adc->CR & ADC_CR_ADEN) {
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if (adc->CR & ADC_CR_ADSTART) {
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adc->CR |= ADC_CR_ADSTP;
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while (adc->CR & ADC_CR_ADSTP)
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;
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}
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/* adc->CR |= ADC_CR_ADDIS;
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while (adc->CR & ADC_CR_ADDIS)
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;*/
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}
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}
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void adc_interrupt(ADC_TypeDef *adc)
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{
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uint32_t isr = adc->ISR;
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adc->ISR = isr;
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if (isr & ADC_ISR_OVR) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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handle_touch_interrupt();
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}
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}
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OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER)
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{
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OSAL_IRQ_PROLOGUE();
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adc_interrupt(ADC1);
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OSAL_IRQ_EPILOGUE();
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}
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