mirror of
https://github.com/ttrftech/NanoVNA.git
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23c765b719
!!!!! Don`t understand why si5351 non stable on band 2 then change from band 3 It fixed if set before sweep one frequency from band 1 (for example 50MHz) Possibly problem in tlv320aic3204_set_gain, call only si5351_set_frequency_with_offset not work Little faster call command from shell Fix interpolation if points < POINTS_COUNT
451 lines
16 KiB
C
451 lines
16 KiB
C
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* Modified by DiSlord dislordlive@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hal.h"
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#include "nanovna.h"
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#include "si5351.h"
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// Enable cache for SI5351 CLKX_CONTROL register, little speedup exchange
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#define USE_CLK_CONTROL_CACHE TRUE
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// XTAL frequency on si5351
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#define XTALFREQ 26000000U
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// MCLK (processor clock if set, audio codec) frequency clock
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#define CLK2_FREQUENCY 8000000U
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// Fixed PLL mode multiplier (used in band 1)
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#define PLL_N 32
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// I2C address on bus (only 0x60 for Si5351A in 10-Pin MSOP)
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#define SI5351_I2C_ADDR 0x60
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static uint8_t current_band = 0;
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static uint32_t current_freq = 0;
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static int32_t current_offset = FREQUENCY_OFFSET;
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// Minimum value is 2, freq change apply at next dsp measure, and need skip it
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#define DELAY_NORMAL 2
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// Delay for bands (depend set band 1 more fast (can change before next dsp buffer ready, need wait additional interval)
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#define DELAY_BAND_1 3
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#define DELAY_BAND_2 2
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// Band changes need set delay after reset PLL
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#define DELAY_BANDCHANGE_1 3
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#define DELAY_BANDCHANGE_2 3
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// Delay after set new PLL values, and send reset (on band 1 unstable if less then 900, on 4000-5000 no amplitude spike on change)
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#define DELAY_RESET_PLL 5000
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uint32_t si5351_getFrequency(void) {return current_freq;}
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void si5351_set_frequency_offset(int32_t offset) {
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current_offset = offset;
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current_freq = 0; // reset freq, for
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}
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static void
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si5351_bulk_write(const uint8_t *buf, int len)
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{
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i2cAcquireBus(&I2CD1);
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(void)i2cMasterTransmitTimeout(&I2CD1, SI5351_I2C_ADDR, buf, len, NULL, 0, 1000);
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i2cReleaseBus(&I2CD1);
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}
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#if 0
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static bool si5351_bulk_read(uint8_t reg, uint8_t* buf, int len)
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{
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i2cAcquireBus(&I2CD1);
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msg_t mr = i2cMasterTransmitTimeout(&I2CD1, SI5351_I2C_ADDR, ®, 1, buf, len, 1000);
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i2cReleaseBus(&I2CD1);
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return mr == MSG_OK;
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}
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static void si5351_wait_pll_lock(void)
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{
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uint8_t status;
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int count = 100;
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do{
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status=0xFF;
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si5351_bulk_read(0, &status, 1);
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if ((status & 0x60) == 0) // PLLA and PLLB locked
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return;
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}while (--count);
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}
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#endif
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static inline void
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si5351_write(uint8_t reg, uint8_t dat)
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{
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uint8_t buf[] = { reg, dat };
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si5351_bulk_write(buf, 2);
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}
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// register addr, length, data, ...
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const uint8_t si5351_configs[] = {
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff,
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4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN,
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2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF,
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// All of this init code run late on sweep
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#if 0
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// setup PLL (26MHz * 32 = 832MHz, 32/2-2=14)
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9, SI5351_REG_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0,
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9, SI5351_REG_PLL_B, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0,
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// RESET PLL
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2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B | 0x0C, //
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// setup multisynth (832MHz / 104 = 8MHz, 104/2-2=50)
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9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0,
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2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE,
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#endif
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, ~(SI5351_CLK0_EN|SI5351_CLK1_EN|SI5351_CLK2_EN),
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0 // sentinel
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};
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void
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si5351_init(void)
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{
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const uint8_t *p = si5351_configs;
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while (*p) {
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uint8_t len = *p++;
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si5351_bulk_write(p, len);
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p += len;
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}
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}
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static const uint8_t disable_output[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_CLK_POWERDOWN, // CLK 0
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SI5351_CLK_POWERDOWN, // CLK 1
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SI5351_CLK_POWERDOWN // CLK 2
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};
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/* Get the appropriate starting point for the PLL registers */
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static const uint8_t msreg_base[] = {
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SI5351_REG_42_MULTISYNTH0,
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SI5351_REG_50_MULTISYNTH1,
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SI5351_REG_58_MULTISYNTH2,
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};
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static const uint8_t clkctrl[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_REG_17_CLK1_CONTROL,
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SI5351_REG_18_CLK2_CONTROL
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};
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// Reset PLL need then band changes
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static void si5351_reset_pll(uint8_t mask)
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{
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// Writing a 1<<5 will reset PLLA, 1<<7 reset PLLB, this is a self clearing bits.
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// !!! Need delay before reset PLL for apply PLL freq changes before
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chThdSleepMicroseconds(DELAY_RESET_PLL);
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si5351_write(SI5351_REG_177_PLL_RESET, mask | 0x0C);
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}
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void si5351_disable_output(void)
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{
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xFF);
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si5351_bulk_write(disable_output, sizeof(disable_output));
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current_band = 0;
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}
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void si5351_enable_output(void)
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{
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, ~(SI5351_CLK0_EN|SI5351_CLK1_EN|SI5351_CLK2_EN));
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//si5351_reset_pll(SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
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current_freq = 0;
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current_band = 0;
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}
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// Set PLL freq = XTALFREQ * (mult + num/denom)
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static void si5351_setupPLL(uint8_t pllSource, /* SI5351_REG_PLL_A or SI5351_REG_PLL_B */
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uint32_t mult,
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uint32_t num,
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uint32_t denom)
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{
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/* Feedback Multisynth Divider Equation
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* where: a = mult, b = num and c = denom
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* P1 register is an 18-bit value using following formula:
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* P1[17:0] = 128 * mult + int((128*num)/denom) - 512
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* P2 register is a 20-bit value using the following formula:
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* P2[19:0] = (128 * num) % denom
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* P3 register is a 20-bit value using the following formula:
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* P3[19:0] = denom
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*/
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/* Set the main PLL config registers */
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mult<<=7;
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num<<=7;
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uint32_t P1 = mult - 512; // Integer mode
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uint32_t P2 = 0;
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uint32_t P3 = 1;
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if (num){ // Fractional mode
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P1+= num / denom;
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P2 = num % denom;
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P3 = denom;
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}
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// Pll MSN(A|B) registers Datasheet
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uint8_t reg[9];
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reg[0]= pllSource; // SI5351_REG_PLL_A or SI5351_REG_PLL_B
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reg[1]=( P3 & 0x0FF00)>> 8; // MSN_P3[15: 8]
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reg[2]=( P3 & 0x000FF); // MSN_P3[ 7: 0]
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reg[3]=( P1 & 0x30000)>>16; // MSN_P1[17:16]
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reg[4]=( P1 & 0x0FF00)>> 8; // MSN_P1[15: 8]
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reg[5]=( P1 & 0x000FF); // MSN_P1[ 7: 0]
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reg[6]=((P3 & 0xF0000)>>12)|((P2 & 0xF0000)>>16); // MSN_P3[19:16] | MSN_P2[19:16]
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reg[7]=( P2 & 0x0FF00)>> 8; // MSN_P2[15: 8]
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reg[8]=( P2 & 0x000FF); // MSN_P2[ 7: 0]
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si5351_bulk_write(reg, 9);
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}
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// Set Multisynth divider = (div + num/denom) * rdiv
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static void
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si5351_setupMultisynth(uint8_t channel,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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uint32_t rdiv, // SI5351_R_DIV_1~128
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uint8_t chctrl) // SI5351_REG_16_CLKX_CONTROL settings
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{
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/* Output Multisynth Divider Equations
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* where: a = div, b = num and c = denom
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* P1 register is an 18-bit value using following formula:
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* P1[17:0] = 128 * a + int((128*b)/c) - 512
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* P2 register is a 20-bit value using the following formula:
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* P2[19:0] = (128 * b) % c
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* P3 register is a 20-bit value using the following formula:
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* P3[19:0] = c
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*/
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/* Set the main PLL config registers */
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uint32_t P1 = 0;
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uint32_t P2 = 0;
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uint32_t P3 = 1;
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if (div == 4)
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rdiv|= SI5351_DIVBY4;
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else {
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num<<=7;
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div<<=7;
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P1 = div - 512; // Integer mode
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if (num){ // Fractional mode
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P1+= num / denom;
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P2 = num % denom;
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P3 = denom;
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}
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}
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/* Set the MSx config registers */
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uint8_t reg[9];
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reg[0]= msreg_base[channel]; // SI5351_REG_42_MULTISYNTH0, SI5351_REG_50_MULTISYNTH1, SI5351_REG_58_MULTISYNTH2
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reg[1]=( P3 & 0x0FF00)>>8; // MSx_P3[15: 8]
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reg[2]=( P3 & 0x000FF); // MSx_P3[ 7: 0]
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reg[3]=((P1 & 0x30000)>>16)| rdiv; // Rx_DIV[2:0] | MSx_DIVBY4[1:0] | MSx_P1[17:16]
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reg[4]=( P1 & 0x0FF00)>> 8; // MSx_P1[15: 8]
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reg[5]=( P1 & 0x000FF); // MSx_P1[ 7: 0]
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reg[6]=((P3 & 0xF0000)>>12)|((P2 & 0xF0000)>>16); // MSx_P3[19:16] | MSx_P2[19:16]
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reg[7]=( P2 & 0x0FF00)>>8; // MSx_P2[15: 8]
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reg[8]=( P2 & 0x000FF); // MSx_P2[ 7: 0]
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si5351_bulk_write(reg, 9);
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/* Configure the clk control and enable the output */
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uint8_t dat = chctrl | SI5351_CLK_INPUT_MULTISYNTH_N;
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if (num == 0)
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dat |= SI5351_CLK_INTEGER_MODE;
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#if USE_CLK_CONTROL_CACHE == TRUE
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// Use cache for this reg, not update if not change
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static uint8_t clk_cache[3];
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if (clk_cache[channel]!=dat){
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si5351_write(clkctrl[channel], dat);
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clk_cache[channel]=dat;
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}
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#else
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si5351_write(clkctrl[channel], dat);
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#endif
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}
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// Find better approximate values for n/d
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#define MAX_DENOMINATOR ((1 << 20) - 1)
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static inline void fractionalSolve(uint32_t *n, uint32_t *d){
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// cf. https://github.com/python/cpython/blob/master/Lib/fractions.py#L227
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uint32_t denom = *d;
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if (denom > MAX_DENOMINATOR) {
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uint32_t num = *n;
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uint32_t p0 = 0, q0 = 1, p1 = 1, q1 = 0;
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while (denom != 0) {
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uint32_t a = num / denom;
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uint32_t b = num % denom;
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uint32_t q2 = q0 + a*q1;
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if (q2 > MAX_DENOMINATOR)
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break;
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uint32_t p2 = p0 + a*p1;
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p0 = p1; q0 = q1; p1 = p2; q1 = q2;
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num = denom; denom = b;
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}
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*n = p1;
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*d = q1;
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}
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}
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// Setup Multisynth divider for get correct output freq if fixed PLL = pllfreq
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static void
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si5351_set_frequency_fixedpll(uint8_t channel, uint64_t pllfreq, uint32_t freq, uint32_t rdiv, uint8_t chctrl)
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{
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uint32_t denom = freq;
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uint32_t div = pllfreq / denom; // range: 8 ~ 1800
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uint32_t num = pllfreq % denom;
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fractionalSolve(&num, &denom);
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si5351_setupMultisynth(channel, div, num, denom, rdiv, chctrl);
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}
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// Setup PLL freq if Multisynth divider fixed = div (need get output = freq/mul)
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static void
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si5351_setupPLL_freq(uint32_t pllSource, uint32_t freq, uint32_t div, uint32_t mul){
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uint32_t denom = XTALFREQ * mul;
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uint64_t pllfreq = (uint64_t)freq * div;
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uint32_t multi = pllfreq / denom;
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uint32_t num = pllfreq % denom;
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fractionalSolve(&num, &denom);
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si5351_setupPLL(pllSource, multi, num, denom);
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}
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#if 0
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static void
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si5351_set_frequency_fixeddiv(uint8_t channel, uint32_t pll, uint32_t freq, uint32_t div,
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uint8_t chctrl, uint32_t mul)
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{
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si5351_setupPLL_freq(pll, freq, div, mul);
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si5351_setupMultisynth(channel, div, 0, 1, SI5351_R_DIV_1, chctrl);
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}
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void
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si5351_set_frequency(int channel, uint32_t freq, uint8_t drive_strength){
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if (freq <= 100000000) {
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si5351_setupPLL(SI5351_PLL_B, 32, 0, 1);
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si5351_set_frequency_fixedpll(channel, SI5351_PLL_B, PLLFREQ, freq, SI5351_R_DIV_1, drive_strength, 1);
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} else if (freq < 150000000) {
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_B, freq, 6, drive_strength, 1);
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} else {
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_B, freq, 4, drive_strength, 1);
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}
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}
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#endif
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/*
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* Frequency generation divide on 3 band
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* Band 1
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* 1~100MHz fixed PLL = XTALFREQ * PLL_N, fractional divider
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* Band 2
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* 100~150MHz fractional PLL = 600- 900MHz, fixed divider 'fdiv = 6'
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* Band 3
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* 150~300MHz fractional PLL = 600-1200MHz, fixed divider 'fdiv = 4'
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*
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* For FREQ_HARMONICS = 300MHz - band range is:
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* +-----------------------------------------------------------------------------------------------------------------------+
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* | Band 1 | Band 2 | Band 3 | Band 2 | Band 3 |
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* +-----------------------------------------------------------------------------------------------------------------------+
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* | Direct mode x1 : x1 | x3 : x5 | x5-x7 | x7-x9 | x9-x11 |
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* +-----------------------------------------------------------------------------------------------------------------------+
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* | 50kHz - 100MHz | 100 - 150MHz | 150 - 300MHz | 300-450MHz | 450-900MHz | 900-1500MHz | 1500-2100MHz | 2100-2700MHz |
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* +-----------------------------------------------------------------------------------------------------------------------+
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* | f = 50kHz-300MHz | f=100-150 | f=150-300 | f=150-300 | f=214-300 | f=233-300 |
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* | of = 50kHz-300MHz |of= 60- 90 |of= 90-180 |of=128-215 |of=166-234 |of=190-246 |
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* +-----------------------------------------------------------------------------------------------------------------------+
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*/
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static inline uint8_t si5351_getBand(uint32_t freq){
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if (freq < 100000000U) return 1;
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if (freq < 150000000U) return 2;
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return 3;
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}
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/*
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* Maximum supported frequency = FREQ_HARMONICS * 9U
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* configure output as follows:
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* CLK0: frequency + offset
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* CLK1: frequency
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* CLK2: fixed 8MHz
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*/
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int
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si5351_set_frequency_with_offset(uint32_t freq, uint8_t drive_strength){
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uint8_t band;
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int delay = DELAY_NORMAL;
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if (freq == current_freq)
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return delay;
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uint32_t ofreq = freq + current_offset;
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uint32_t mul = 1, omul = 1;
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uint32_t rdiv = SI5351_R_DIV_1;
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uint32_t fdiv;
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// Fix possible uncorrect input
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drive_strength&=SI5351_CLK_DRIVE_STRENGTH_MASK;
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current_freq = freq;
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if (freq >= config.harmonic_freq_threshold * 7U) {
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mul = 9;
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omul = 11;
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} else if (freq >= config.harmonic_freq_threshold * 5U) {
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mul = 7;
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omul = 9;
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} else if (freq >= config.harmonic_freq_threshold * 3U) {
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mul = 5;
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omul = 7;
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} else if (freq >= config.harmonic_freq_threshold) {
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mul = 3;
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omul = 5;
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}
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else if (freq <= 500000U) {
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rdiv = SI5351_R_DIV_64;
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freq<<= 6;
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ofreq<<= 6;
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} else if (freq <= 4000000U) {
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rdiv = SI5351_R_DIV_8;
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freq<<= 3;
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ofreq<<= 3;
|
|
}
|
|
band = si5351_getBand(freq/mul);
|
|
switch (band) {
|
|
case 1:
|
|
// Setup CH0 and CH1 constant PLLA freq at band change, and set CH2 freq = CLK2_FREQUENCY
|
|
if (current_band != 1){
|
|
si5351_setupPLL(SI5351_REG_PLL_A, PLL_N, 0, 1);
|
|
si5351_set_frequency_fixedpll(2, XTALFREQ * PLL_N, CLK2_FREQUENCY, SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA|SI5351_CLK_PLL_SELECT_A);
|
|
delay=DELAY_BANDCHANGE_1;
|
|
}
|
|
else
|
|
delay=DELAY_BAND_1;
|
|
// Calculate and set CH0 and CH1 divider
|
|
si5351_set_frequency_fixedpll(0, (uint64_t)omul * XTALFREQ * PLL_N, ofreq, rdiv, drive_strength|SI5351_CLK_PLL_SELECT_A);
|
|
si5351_set_frequency_fixedpll(1, (uint64_t) mul * XTALFREQ * PLL_N, freq, rdiv, drive_strength|SI5351_CLK_PLL_SELECT_A);
|
|
break;
|
|
case 2:// fdiv = 6
|
|
case 3:// fdiv = 4;
|
|
fdiv = (band == 2) ? 6 : 4;
|
|
// Setup CH0 and CH1 constant fdiv divider at change
|
|
if (current_band != band){
|
|
si5351_setupMultisynth(0, fdiv, 0, 1, SI5351_R_DIV_1, drive_strength|SI5351_CLK_PLL_SELECT_A);
|
|
si5351_setupMultisynth(1, fdiv, 0, 1, SI5351_R_DIV_1, drive_strength|SI5351_CLK_PLL_SELECT_B);
|
|
delay=DELAY_BANDCHANGE_2;
|
|
}
|
|
else
|
|
delay=DELAY_BAND_2;
|
|
// Calculate and set CH0 and CH1 PLL freq
|
|
si5351_setupPLL_freq(SI5351_REG_PLL_A, ofreq, fdiv, omul);// set PLLA freq = (ofreq/omul)*fdiv
|
|
si5351_setupPLL_freq(SI5351_REG_PLL_B, freq, fdiv, mul);// set PLLB freq = ( freq/ mul)*fdiv
|
|
// Calculate CH2 freq = CLK2_FREQUENCY, depend from calculated before CH1 PLLB = (freq/mul)*fdiv
|
|
si5351_set_frequency_fixedpll(2, (uint64_t)freq*fdiv, CLK2_FREQUENCY*mul, SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA|SI5351_CLK_PLL_SELECT_B);
|
|
break;
|
|
}
|
|
if (current_band != band) {
|
|
si5351_reset_pll(SI5351_PLL_RESET_A|SI5351_PLL_RESET_B);
|
|
current_band = band;
|
|
}
|
|
return delay;
|
|
}
|