mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
a43b6e3acc
Cleanup and optimize code Add comments, fix definitions Fix rounding errors Fix band 1 stability mcuconf.h Set I2C bus clock to SYSCLK (more fast) Apply 400kHz bus I2C clock timings for 8MHz and 48Mhz clock main.c Remove and reset some variables Add separate sweep for calibration (allow calibrate if sweep paused) Increase main thread stack (need for run calibrate, possibly need execute some commands in sweep threads for reduce stack usage)
76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#define SI5351_REG_3_OUTPUT_ENABLE_CONTROL 3
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#define SI5351_CLK0_EN (1<<0)
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#define SI5351_CLK1_EN (1<<1)
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#define SI5351_CLK2_EN (1<<2)
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// Reg 16-18 CLKX_CONTROL
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#define SI5351_REG_16_CLK0_CONTROL 16
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#define SI5351_REG_17_CLK1_CONTROL 17
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#define SI5351_REG_18_CLK2_CONTROL 18
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#define SI5351_CLK_POWERDOWN (1<<7)
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#define SI5351_CLK_INTEGER_MODE (1<<6)
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#define SI5351_CLK_PLL_SELECT_A (0<<5)
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#define SI5351_CLK_PLL_SELECT_B (1<<5)
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#define SI5351_CLK_INVERT (1<<4)
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#define SI5351_CLK_INPUT_MASK (3<<2)
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#define SI5351_CLK_INPUT_XTAL (0<<2)
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#define SI5351_CLK_INPUT_CLKIN (1<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
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#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
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#define SI5351_REG_PLL_A 26
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#define SI5351_REG_PLL_B 34
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#define SI5351_REG_42_MULTISYNTH0 42
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#define SI5351_REG_50_MULTISYNTH1 50
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#define SI5351_REG_58_MULTISYNTH2 58
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#define SI5351_DIVBY4 (3<<2)
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#define SI5351_R_DIV_1 (0<<4)
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#define SI5351_R_DIV_2 (1<<4)
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#define SI5351_R_DIV_4 (2<<4)
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#define SI5351_R_DIV_8 (3<<4)
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#define SI5351_R_DIV_16 (4<<4)
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#define SI5351_R_DIV_32 (5<<4)
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#define SI5351_R_DIV_64 (6<<4)
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#define SI5351_R_DIV_128 (7<<4)
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#define SI5351_REG_177_PLL_RESET 177
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#define SI5351_PLL_RESET_B (1<<7)
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#define SI5351_PLL_RESET_A (1<<5)
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#define SI5351_REG_183_CRYSTAL_LOAD 183
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#define SI5351_CRYSTAL_LOAD_6PF (1<<6)
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#define SI5351_CRYSTAL_LOAD_8PF (2<<6)
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#define SI5351_CRYSTAL_LOAD_10PF (3<<6)
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void si5351_init(void);
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void si5351_disable_output(void);
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void si5351_enable_output(void);
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//void si5351_set_frequency(int channel, uint32_t freq, uint8_t drive_strength);
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int si5351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_strength);
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