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https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
make fast si5351 i2c control, add scan command
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TT
parent
7c4c5a76dc
commit
c84d5f0fa5
25
dsp.c
25
dsp.c
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@ -41,7 +41,6 @@ hilbert_transform(void)
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int32_t accn0 = 0;
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int32_t acc1 = 0;
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int32_t accn1 = 0;
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int32_t s;
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for (i = 0; i < 8; i += 2) {
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uint32_t c = *(uint32_t*)&hilbert31_coeffs[i];
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@ -75,6 +74,7 @@ hilbert_transform(void)
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}
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void calclate_gamma(void)
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#if 0
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{
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__SIMD32_TYPE *r = __SIMD32_CONST(refiq_buf);
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__SIMD32_TYPE *s = __SIMD32_CONST(samp_buf);
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@ -98,7 +98,30 @@ void calclate_gamma(void)
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gamma_real = acc_r / 65536;
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gamma_imag = acc_i / 65536;
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}
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#else
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{
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int16_t *r = refiq_buf;
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int16_t *s = samp_buf;
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int len = SAMPLE_LEN/5;
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double acc_r = 0;
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double acc_i = 0;
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double acc_ref = 0;
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int i;
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double rn;
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for (i = 0; i < len; i++) {
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int16_t s0 = *s++;
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int16_t rr = *r++;
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int16_t ri = *r++;
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acc_r += (double)(s0 * rr);
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acc_i += (double)(s0 * ri);
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acc_ref += (double)rr*rr + (double)ri*ri;
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}
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rn = sqrtf(acc_ref / len);
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gamma_real = 16 * acc_r / rn / len;
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gamma_imag = 16 * acc_i / rn / len;
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}
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#endif
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void
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dsp_process(int16_t *capture, size_t length)
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59
main.c
59
main.c
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@ -13,7 +13,8 @@ RTCDateTime timespec;
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static const I2CConfig i2ccfg = {
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0x00902025, //voodoo magic
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0x00300506, //voodoo magic 400kHz @ HSI 8MHz
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//0x00902025, //voodoo magic
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//0x00420F13, // 100kHz @ 72MHz
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0,
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0
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@ -143,14 +144,7 @@ static void cmd_dac(BaseSequentialStream *chp, int argc, char *argv[])
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return;
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}
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value = atoi(argv[0]);
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#if 1
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dacPutChannelX(&DACD2, 0, value);
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#else
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if (value & 1)
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palSetPad(GPIOA, 5);
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else
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palClearPad(GPIOA, 5);
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#endif
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}
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@ -187,7 +181,7 @@ void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n)
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int16_t *p = &rx_buffer[offset];
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(void)i2sp;
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(void)n;
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palClearPad(GPIOC, GPIOC_LED);
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//palClearPad(GPIOC, GPIOC_LED);
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if (!dsp_disabled)
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dsp_process(p, n);
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@ -219,7 +213,7 @@ void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n)
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stat.last_counter_value = cnt_s;
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#endif
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stat.callback_count++;
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palSetPad(GPIOC, GPIOC_LED);
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//palSetPad(GPIOC, GPIOC_LED);
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}
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static const I2SConfig i2sconfig = {
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@ -261,7 +255,7 @@ static void cmd_gamma(BaseSequentialStream *chp, int argc, char *argv[])
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(void)argc;
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(void)argv;
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wait_count = 3;
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wait_count = 4;
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while (wait_count)
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;
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dsp_disabled = TRUE;
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@ -271,6 +265,47 @@ static void cmd_gamma(BaseSequentialStream *chp, int argc, char *argv[])
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chprintf(chp, "%d %d\r\n", gamma_real, gamma_imag);
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}
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static void cmd_scan(BaseSequentialStream *chp, int argc, char *argv[])
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{
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int i;
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int len = 100;
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(void)argc;
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(void)argv;
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for (i = 1; i <= len; i++) {
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int32_t freq = i * 3000000L;
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wait_count = 4;
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while (wait_count)
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;
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dsp_disabled = TRUE;
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set_frequency(freq);
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palClearPad(GPIOC, GPIOC_LED);
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calclate_gamma();
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palSetPad(GPIOC, GPIOC_LED);
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dsp_disabled = FALSE;
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chprintf(chp, "%d %d %d\r\n", freq, gamma_real, gamma_imag);
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}
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}
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static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[])
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{
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int i;
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(void)argc;
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(void)argv;
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for (i = 0; i < 100; i++) {
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palClearPad(GPIOC, GPIOC_LED);
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set_frequency(10000000);
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palSetPad(GPIOC, GPIOC_LED);
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chThdSleepMilliseconds(50);
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palClearPad(GPIOC, GPIOC_LED);
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set_frequency(100000000);
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palSetPad(GPIOC, GPIOC_LED);
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chThdSleepMilliseconds(50);
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}
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}
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static void cmd_gain(BaseSequentialStream *chp, int argc, char *argv[])
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{
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int rvalue;
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@ -352,6 +387,8 @@ static const ShellCommand commands[] =
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{ "gain", cmd_gain },
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{ "power", cmd_power },
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{ "gamma", cmd_gamma },
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{ "scan", cmd_scan },
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{ "test", cmd_test },
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{ NULL, NULL }
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};
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50
si5351.c
50
si5351.c
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@ -53,10 +53,13 @@ si5351_init(void)
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void si5351_disable_output(void)
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{
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uint8_t reg[4];
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff);
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si5351_write(SI5351_REG_16_CLK0_CONTROL, 0x80);
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si5351_write(SI5351_REG_17_CLK1_CONTROL, 0x80);
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si5351_write(SI5351_REG_18_CLK2_CONTROL, 0x80);
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reg[0] = SI5351_REG_16_CLK0_CONTROL;
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reg[1] = SI5351_CLK_POWERDOWN;
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reg[2] = SI5351_CLK_POWERDOWN;
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reg[3] = SI5351_CLK_POWERDOWN;
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si5351_bulk_write(reg, 4);
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}
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void si5351_enable_output(void)
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@ -80,8 +83,6 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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SI5351_REG_26_PLL_A,
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SI5351_REG_34_PLL_B
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};
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uint8_t baseaddr = pllreg_base[pll];
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uint32_t P1;
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uint32_t P2;
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uint32_t P3;
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@ -115,14 +116,17 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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}
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/* The datasheet is a nightmare of typos and inconsistencies here! */
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si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+1, (P3 & 0x000000FF));
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si5351_write(baseaddr+2, (P1 & 0x00030000) >> 16);
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si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+4, (P1 & 0x000000FF));
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si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) );
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si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+7, (P2 & 0x000000FF));
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uint8_t reg[9];
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reg[0] = pllreg_base[pll];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = (P1 & 0x00030000) >> 16;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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}
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void
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@ -139,7 +143,6 @@ si5351_setupMultisynth(uint8_t output,
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SI5351_REG_50_MULTISYNTH1,
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SI5351_REG_58_MULTISYNTH2,
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};
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uint8_t baseaddr = msreg_base[output];
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const uint8_t clkctrl[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_REG_17_CLK1_CONTROL,
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@ -179,14 +182,17 @@ si5351_setupMultisynth(uint8_t output,
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}
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/* Set the MSx config registers */
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si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+1, (P3 & 0x000000FF));
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si5351_write(baseaddr+2, ((P1 & 0x00030000) >> 16) | div4);
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si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+4, (P1 & 0x000000FF));
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si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16));
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si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+7, (P2 & 0x000000FF));
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uint8_t reg[9];
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reg[0] = msreg_base[output];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = ((P1 & 0x00030000) >> 16) | div4;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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/* Configure the clk control and enable the output */
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dat = drive_strength | SI5351_CLK_INPUT_MULTISYNTH_N;
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