mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
add band pass filter on tlv320aic3204
This commit is contained in:
TT
parent
a563484f38
commit
ab87c813a1
24
dsp.c
24
dsp.c
|
|
@ -8,7 +8,7 @@ int16_t refiq_buf[AUDIO_BUFFER_LEN];
|
|||
|
||||
int16_t samp_buf[SAMPLE_LEN];
|
||||
|
||||
|
||||
#if 0
|
||||
// Bi-Quad IIR Filter state
|
||||
q15_t bq_state1[4 * 4];
|
||||
q15_t bq_state2[4 * 4];
|
||||
|
|
@ -22,6 +22,7 @@ q15_t bq_coeffs[] = {
|
|||
|
||||
arm_biquad_casd_df1_inst_q15 bq1 = { 3, bq_state1, bq_coeffs, 1};
|
||||
arm_biquad_casd_df1_inst_q15 bq2 = { 3, bq_state2, bq_coeffs, 1};
|
||||
#endif
|
||||
|
||||
const q15_t hilbert31_coeffs[] = {
|
||||
20570, 6125, 2918, 1456, 682, 279, 91, 19
|
||||
|
|
@ -67,6 +68,7 @@ hilbert_transform(void)
|
|||
src++;
|
||||
}
|
||||
|
||||
/* copy last samples as fir state onto buffer */
|
||||
dst = __SIMD32_CONST(ref_state);
|
||||
for (j = 0; j < STATE_LEN / 2; j++) {
|
||||
*dst++ = *src++;
|
||||
|
|
@ -109,10 +111,24 @@ void calclate_gamma(float *gamma)
|
|||
int i;
|
||||
float rn;
|
||||
|
||||
int32_t offset_s0 = 0;
|
||||
int32_t offset_r0 = 0;
|
||||
int32_t offset_i0 = 0;
|
||||
for (i = 0; i < len; i++) {
|
||||
int16_t s0 = *s++;
|
||||
int16_t ri = *r++;
|
||||
int16_t rr = *r++;
|
||||
offset_s0 += *s++;
|
||||
offset_i0 += *r++;
|
||||
offset_r0 += *r++;
|
||||
}
|
||||
offset_s0 /= len;
|
||||
offset_r0 /= len;
|
||||
offset_i0 /= len;
|
||||
|
||||
r = refiq_buf;
|
||||
s = samp_buf;
|
||||
for (i = 0; i < len; i++) {
|
||||
int16_t s0 = *s++ - offset_s0;
|
||||
int16_t ri = *r++ - offset_i0;
|
||||
int16_t rr = *r++ - offset_r0;
|
||||
acc_r += (float)(s0 * rr);
|
||||
acc_i += (float)(s0 * ri);
|
||||
acc_ref += (float)rr*rr + (float)ri*ri;
|
||||
|
|
|
|||
|
|
@ -559,7 +559,7 @@ trace_t trace[TRACES_MAX] = {
|
|||
{ 1, TRC_LOGMAG, 0, RGB565(0,255,255), 0 },
|
||||
{ 1, TRC_LOGMAG, 1, RGB565(255,0,40), 0 },
|
||||
{ 1, TRC_SMITH, 0, RGB565(0,0,255), 1 },
|
||||
{ 0, TRC_SMITH, 1, RGB565(0,255,0), 1 }
|
||||
{ 1, TRC_PHASE, 1, RGB565(50,255,0), 1 }
|
||||
};
|
||||
|
||||
uint32_t trace_index[TRACES_MAX][101];
|
||||
|
|
@ -731,6 +731,7 @@ trace_into_index(int x, int t, int i, float coeff[2])
|
|||
idx = INDEX(x, y1, i);
|
||||
break;
|
||||
case TRC_SMITH:
|
||||
case TRC_ADMIT:
|
||||
case TRC_POLAR:
|
||||
cartesian_scale(coeff[0], coeff[1], &x1, &y1);
|
||||
idx = INDEX(x1, y1, i);
|
||||
|
|
|
|||
11
main.c
11
main.c
|
|
@ -46,7 +46,7 @@ static MUTEX_DECL(mutex);
|
|||
|
||||
|
||||
|
||||
static THD_WORKING_AREA(waThread1, 400);
|
||||
static THD_WORKING_AREA(waThread1, 384);
|
||||
static THD_FUNCTION(Thread1, arg)
|
||||
{
|
||||
(void)arg;
|
||||
|
|
@ -347,7 +347,7 @@ static void cmd_scan(BaseSequentialStream *chp, int argc, char *argv[])
|
|||
delay += 2;
|
||||
for (i = 0; i < sweep_points; i++) {
|
||||
freq = freq + step;
|
||||
wait_count = delay;
|
||||
wait_count = delay + 1;
|
||||
while (wait_count)
|
||||
;
|
||||
//dsp_disabled = TRUE;
|
||||
|
|
@ -371,7 +371,7 @@ void scan_lcd(void)
|
|||
delay = set_frequency(frequencies[0]);
|
||||
delay += 2;
|
||||
for (i = 0; i < sweep_points; i++) {
|
||||
wait_count = delay;
|
||||
wait_count = delay + 1;
|
||||
tlv320aic3204_select_in3();
|
||||
while (wait_count)
|
||||
;
|
||||
|
|
@ -381,7 +381,7 @@ void scan_lcd(void)
|
|||
__enable_irq();
|
||||
|
||||
tlv320aic3204_select_in1();
|
||||
wait_count = 2;
|
||||
wait_count = 2 + 1;
|
||||
while (wait_count)
|
||||
;
|
||||
__disable_irq();
|
||||
|
|
@ -862,7 +862,7 @@ static void cmd_stat(BaseSequentialStream *chp, int argc, char *argv[])
|
|||
|
||||
|
||||
|
||||
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(400)
|
||||
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(460)
|
||||
|
||||
static const ShellCommand commands[] =
|
||||
{
|
||||
|
|
@ -940,6 +940,7 @@ int main(void)
|
|||
*/
|
||||
ili9341_init();
|
||||
|
||||
/* restore config and calibration data from flash memory */
|
||||
caldata_recall();
|
||||
|
||||
set_sweep(freq_start, freq_stop);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ extern void tlv320aic3204_set_volume(int gain);
|
|||
extern void tlv320aic3204_agc_config(tlv320aic3204_agc_config_t *conf);
|
||||
extern void tlv320aic3204_select_in1(void);
|
||||
extern void tlv320aic3204_select_in3(void);
|
||||
extern void tlv320aic3204_adc_filter_enable(int enable);
|
||||
|
||||
extern void ui_init(void);
|
||||
extern void ui_process(void);
|
||||
|
|
|
|||
165
tlv320aic3204.c
165
tlv320aic3204.c
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#define wait_ms(ms) chThdSleepMilliseconds(ms)
|
||||
|
||||
void tlv320aic3204_config_adc_filter(void);
|
||||
|
||||
void tlv320aic3204_init(void)
|
||||
{
|
||||
|
|
@ -69,6 +70,9 @@ void tlv320aic3204_init(void)
|
|||
I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */
|
||||
I2CWrite(AIC3204_ADDR, 0x51, 0xc0); /* Power up Left and Right ADC Channels */
|
||||
I2CWrite(AIC3204_ADDR, 0x52, 0x00); /* Unmute Left and Right ADC Digital Volume Control */
|
||||
|
||||
tlv320aic3204_config_adc_filter();
|
||||
tlv320aic3204_adc_filter_enable(TRUE);
|
||||
}
|
||||
|
||||
void tlv320aic3204_select_in3(void)
|
||||
|
|
@ -87,6 +91,167 @@ void tlv320aic3204_select_in1(void)
|
|||
I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */
|
||||
}
|
||||
|
||||
void tlv320aic3204_adc_filter_enable(int enable)
|
||||
{
|
||||
if (enable)
|
||||
I2CWrite(AIC3204_ADDR, 0x3d, 0x02); /* Select ADC PRB_R2 */
|
||||
else
|
||||
I2CWrite(AIC3204_ADDR, 0x3d, 0x01); /* Select ADC PRB_R1 */
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* bb, aa = signal.ellip(5, 0.1, 100, (4800.0/24000, 5200.0/24000), 'bandpass') */
|
||||
const uint8_t adc_filter_config[] = {
|
||||
/* len, page, reg, data.... */
|
||||
|
||||
/* left channel C7 - C31 */
|
||||
92, 8, 36,
|
||||
/* Pg8 Reg36-127 */
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf5, 0xeb, 0x1c, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x63, 0x04, 0xf8, 0x00,
|
||||
0x82, 0xf3, 0x20, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf8, 0xac, 0x58, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x64, 0x26, 0x9e, 0x00,
|
||||
0x83, 0x9c, 0x9a, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf5, 0x92, 0x43, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x65, 0xcc, 0x37, 0x00,
|
||||
0x82, 0xd1, 0x6e, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf7, 0xd5, 0x05, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x67, 0x48, 0x63, 0x00,
|
||||
0x81, 0x0a, 0xab, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0xf4, 0x4c, 0x16, 0x00,
|
||||
8, 9, 8,
|
||||
/* Pg9 Reg 8-15 */
|
||||
0x62, 0xdd, 0xc7, 0x00,
|
||||
0x81, 0x1e, 0xf9, 0x00,
|
||||
|
||||
/* right channel C39 - C63 */
|
||||
84, 9, 44,
|
||||
/* Pg9 Reg 44-127 */
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf5, 0xeb, 0x1c, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x63, 0x04, 0xf8, 0x00,
|
||||
0x82, 0xf3, 0x20, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf8, 0xac, 0x58, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x64, 0x26, 0x9e, 0x00,
|
||||
0x83, 0x9c, 0x9a, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf5, 0x92, 0x43, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x65, 0xcc, 0x37, 0x00,
|
||||
0x82, 0xd1, 0x6e, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0xf7, 0xd5, 0x05, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
0x67, 0x48, 0x63, 0x00,
|
||||
0x81, 0x0a, 0xab, 0x00,
|
||||
0x0b, 0xb3, 0xea, 0x00,
|
||||
|
||||
16, 10, 8,
|
||||
/* Pg10 Reg 8-23 */
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0xf4, 0x4c, 0x16, 0x00,
|
||||
0x62, 0xdd, 0xc7, 0x00,
|
||||
0x81, 0x1e, 0xf9, 0x00,
|
||||
0 /* sentinel */
|
||||
};
|
||||
#elsif 0
|
||||
/* bb, aa = signal.ellip(2, 0.1, 100, (4500.0/24000, 5500.0/24000), 'bandpass') */
|
||||
const uint8_t adc_filter_config[] = {
|
||||
/* len, page, reg, data.... */
|
||||
/* left channel C7 - C31 */
|
||||
40, 8, 36,
|
||||
/* Pg8 Reg36-127 */
|
||||
0x02, 0x65, 0xce, 0x00,
|
||||
0x02, 0x65, 0x1b, 0x00,
|
||||
0x02, 0x65, 0xce, 0x00,
|
||||
0x65, 0x27, 0x96, 0x00,
|
||||
0x90, 0x4b, 0xd5, 0x00,
|
||||
0x52, 0x46, 0xbb, 0x00,
|
||||
0xad, 0xb9, 0x96, 0x00,
|
||||
0x52, 0x46, 0xbb, 0x00,
|
||||
0x56, 0x5f, 0xd2, 0x00,
|
||||
0x94, 0x52, 0x41, 0x00,
|
||||
/* right channel C39 - C63 */
|
||||
40, 9, 44,
|
||||
/* Pg9 Reg 44-127 */
|
||||
0x02, 0x65, 0xce, 0x00,
|
||||
0x02, 0x65, 0x1b, 0x00,
|
||||
0x02, 0x65, 0xce, 0x00,
|
||||
0x65, 0x27, 0x96, 0x00,
|
||||
0x90, 0x4b, 0xd5, 0x00,
|
||||
0x52, 0x46, 0xbb, 0x00,
|
||||
0xad, 0xb9, 0x96, 0x00,
|
||||
0x52, 0x46, 0xbb, 0x00,
|
||||
0x56, 0x5f, 0xd2, 0x00,
|
||||
0x94, 0x52, 0x41, 0x00,
|
||||
0 /* sentinel */
|
||||
};
|
||||
#else
|
||||
/* bb, aa = signal.bessel(2, (4500.0/24000, 5500.0/24000), 'bandpass') */
|
||||
const uint8_t adc_filter_config[] = {
|
||||
/* len, page, reg, data.... */
|
||||
/* left channel C7 - C31 */
|
||||
40, 8, 36,
|
||||
/* Pg8 Reg36-127 */
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x5d, 0x91, 0x0f, 0x00,
|
||||
0x8e, 0x4b, 0x9a, 0x00,
|
||||
0x18, 0x22, 0x1d, 0x00,
|
||||
0xe7, 0xdd, 0xe3, 0x00,
|
||||
0x18, 0x22, 0x1d, 0x00,
|
||||
0x62, 0xd9, 0x9b, 0x00,
|
||||
0x8d, 0x2c, 0xda, 0x00,
|
||||
|
||||
/* right channel C39 - C63 */
|
||||
40, 9, 44,
|
||||
/* Pg9 Reg 44-127 */
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x02, 0x9b, 0xed, 0x00,
|
||||
0x5d, 0x91, 0x0f, 0x00,
|
||||
0x8e, 0x4b, 0x9a, 0x00,
|
||||
0x18, 0x22, 0x1d, 0x00,
|
||||
0xe7, 0xdd, 0xe3, 0x00,
|
||||
0x18, 0x22, 0x1d, 0x00,
|
||||
0x62, 0xd9, 0x9b, 0x00,
|
||||
0x8d, 0x2c, 0xda, 0x00,
|
||||
0 /* sentinel */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
void tlv320aic3204_config_adc_filter(void)
|
||||
{
|
||||
const uint8_t *p = adc_filter_config;
|
||||
|
||||
while (*p != 0) {
|
||||
uint8_t len = *p++;
|
||||
uint8_t page = *p++;
|
||||
uint8_t reg = *p++;
|
||||
I2CWrite(AIC3204_ADDR, 0x00, page);
|
||||
while (len-- > 0)
|
||||
I2CWrite(AIC3204_ADDR, reg++, *p++);
|
||||
}
|
||||
I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* page 0 */
|
||||
}
|
||||
|
||||
|
||||
void tlv320aic3204_set_gain(int lgain, int rgain)
|
||||
{
|
||||
if (lgain < 0)
|
||||
|
|
|
|||
Loading…
Reference in a new issue