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add band change handling

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TT 2016-09-24 10:25:13 +09:00
parent c84d5f0fa5
commit a5fd502ba0
3 changed files with 68 additions and 23 deletions
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34
main.c
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@ -76,14 +76,17 @@ int32_t frequency_offset = 5000;
int32_t frequency = 10000000;
uint8_t drive_strength = SI5351_CLK_DRIVE_STRENGTH_2MA;
void set_frequency(int freq)
int set_frequency(int freq)
{
frequency = freq;
#if 0
si5351_set_frequency(0, freq + frequency_offset);
si5351_set_frequency(1, freq);
frequency = freq;
#else
si5351_set_frequency_with_offset(freq, frequency_offset, drive_strength);
int delay;
delay = si5351_set_frequency_with_offset(freq, frequency_offset, drive_strength);
frequency = freq;
return delay;
#endif
}
@ -269,21 +272,30 @@ static void cmd_scan(BaseSequentialStream *chp, int argc, char *argv[])
{
int i;
int len = 100;
int32_t freq, cur_freq, step;
int delay;
(void)argc;
(void)argv;
for (i = 1; i <= len; i++) {
int32_t freq = i * 3000000L;
wait_count = 4;
freq = 3000000;
step = 3000000;
delay = set_frequency(freq);
delay += 2;
for (i = 0; i < len; i++) {
cur_freq = freq;
freq = freq + step;
wait_count = delay;
while (wait_count)
;
dsp_disabled = TRUE;
set_frequency(freq);
//dsp_disabled = TRUE;
__disable_irq();
delay = set_frequency(freq);
palClearPad(GPIOC, GPIOC_LED);
calclate_gamma();
palSetPad(GPIOC, GPIOC_LED);
dsp_disabled = FALSE;
chprintf(chp, "%d %d %d\r\n", freq, gamma_real, gamma_imag);
//dsp_disabled = FALSE;
__enable_irq();
chprintf(chp, "%d %d %d\r\n", cur_freq, gamma_real, gamma_imag);
}
}
@ -300,7 +312,7 @@ static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[])
chThdSleepMilliseconds(50);
palClearPad(GPIOC, GPIOC_LED);
set_frequency(100000000);
set_frequency(90000000);
palSetPad(GPIOC, GPIOC_LED);
chThdSleepMilliseconds(50);
}

2
nanovna.h
View file

@ -43,4 +43,4 @@ extern int32_t gamma_imag;
void dsp_process(int16_t *src, size_t len);
void calclate_gamma(void);
void si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength);
int si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength);

55
si5351.c
View file

@ -273,6 +273,9 @@ si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
}
}
int current_band = -1;
/*
* configure output as follows:
* CLK0: frequency + offset
@ -280,33 +283,63 @@ si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
* CLK2: fixed 8MHz
*/
#define CLK2_FREQUENCY 8000000L
void
int
si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
{
si5351_disable_output();
int band;
int delay = 1;
if (freq <= 100000000) {
band = 0;
} else if (freq < 150000000) {
band = 1;
} else {
band = 2;
}
if (current_band != band)
si5351_disable_output();
switch (band) {
case 0:
// fractional divider mode. only PLL A is used.
si5351_setupPLL(SI5351_PLL_A, 32, 0, 1);
//if (current_band != 0)
si5351_setupPLL(SI5351_PLL_A, 32, 0, 1);
si5351_set_frequency_fixedpll(0, SI5351_PLL_A, PLLFREQ, freq + offset,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixedpll(1, SI5351_PLL_A, PLLFREQ, freq, drive_strength);
si5351_set_frequency_fixedpll(2, SI5351_PLL_A, PLLFREQ, CLK2_FREQUENCY,
SI5351_CLK_DRIVE_STRENGTH_2MA);
} else if (freq < 150000000) {
//if (current_band != 0)
si5351_set_frequency_fixedpll(2, SI5351_PLL_A, PLLFREQ, CLK2_FREQUENCY,
SI5351_CLK_DRIVE_STRENGTH_2MA);
//delay = 1;
delay = 2;
break;
case 1:
// div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
SI5351_CLK_DRIVE_STRENGTH_2MA);
} else {
delay = 2;
break;
case 2:
// div by 4 mode. both PLL A and B are dedicated for CLK0, CLK1
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 4,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 4,
SI5351_CLK_DRIVE_STRENGTH_2MA);
delay = 2;
break;
}
si5351_reset_pll();
si5351_enable_output();
if (current_band != band) {
si5351_reset_pll();
si5351_enable_output();
delay += 5;
}
current_band = band;
return delay;
}