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https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
Add support 96kHz ADC, allow increase sweep speed and bandwidth to 2kHz
This commit is contained in:
DiSlord
parent
23475a75c4
commit
a1bbee724c
184
tlv320aic3204.c
184
tlv320aic3204.c
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@ -20,7 +20,6 @@
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#include "hal.h"
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#include "nanovna.h"
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#define REFCLK_8000KHZ
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#define AIC3204_ADDR 0x18
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#define wait_ms(ms) chThdSleepMilliseconds(ms)
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@ -110,77 +109,124 @@
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#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0)
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static const uint8_t conf_data[] = {
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// reg, data,
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// PLL clock config
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0x00, 0x00, /* Initialize to Page 0 */
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0x01, 0x01, /* Initialize the device through software reset */
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0x04, 0x43, /* PLL Clock High, MCLK, PLL */
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#ifdef REFCLK_8000KHZ
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/* 8.000MHz*10.7520 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */
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0x05, 0x91, /* Power up PLL, P=1,R=1 */
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0x06, 0x0a, /* J=10 */
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0x07, 29, /* D=7520 = (29<<8) + 96 */
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0x08, 96,
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// reg, data, // PLL clock config
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0x00, 0x00, // Initialize to Page 0
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0x01, 0x01, // Initialize the device through software reset
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0x04, 0x03, // PLL Clock Low (80MHz - 137MHz), MCLK, PLL
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//=======================================================
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// Configure PLL clock
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// PLL_CLKIN * R * J.D
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// PLL_CLK = ---------------------
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// P
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#if AUDIO_CLOCK_REF == 8000000U
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// 8.000MHz * 10.7520 = 86.016MHz,
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0x05, 0x91, // Power up PLL, P=1,R=1
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0x06, 0x0a, // J=10
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0x07, 0x1D, // D=7520 = 0x1D60
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0x08, 0x60,
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#elif AUDIO_CLOCK_REF == 10752000U
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// 10.752MHz * 4 * 2.0 / 1 = 86.016MHz
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0x05, 0x94, // Power up PLL, P=1,R=4
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0x06, 0x02, // J=2
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0x07, 0x00, // D=0
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0x08, 0x00,
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#else
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#error "Need set correct PLL multiplier for aic3204"
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#endif
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// Configure ADC clock
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// PLL_CLK
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// ADC_fs = --------------------
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// NADC * MADC * AOSR
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#if AUDIO_ADC_FREQ == 48000
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// Clock config, default fs=48kHz
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// from PLL 86.016MHz/(2*7*128) = 48kHz
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0x0b, 0x82, // Power up the NDAC divider with value 2
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0x0c, 0x87, // Power up the MDAC divider with value 7
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 128
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0x0e, 0x80, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power down
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0x12, 0x82, // Power up the NADC divider with value 2
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x80, // ADC Oversampling (AOSR) Program the OSR of ADC to 128
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0x3d, 0x01, // Select ADC PRB_R1
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 28,// Enable the BCLKN divider with value 28 (I2S clock = 86.016MHz/(NDAC*28) = 48kHz * (16+16)
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#elif AUDIO_ADC_FREQ == 96000
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// Clock config, default fs=96kHz
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// from PLL 86.016MHz/(2*7*64) = 96kHz
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0x0b, 0x82, // Power up the NDAC divider with value 2
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0x0c, 0x87, // Power up the MDAC divider with value 7
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 64
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0x0e, 0x40, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power up
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0x12, 0x82, // Power up the NADC divider with value 2
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x40, // ADC Oversampling (AOSR) set OSR of ADC to 64
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0x3d, 0x01, // Select ADC PRB_R1 (AOSR = 64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B))
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16)
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#else
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#error "Need set correct ADC clock for aic3204"
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#endif
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// Clock config, default fs=48kHz
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0x0b, 0x82, /* Power up the NDAC divider with value 2 */
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0x0c, 0x87, /* Power up the MDAC divider with value 7 */
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0x0d, 0x00, /* Program the OSR of DAC to 128 */
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0x0e, 0x80,
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0x3c, 0x08, /* Set the DAC Mode to PRB_P8 */
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//0x3c, 25, /* Set the DAC Mode to PRB_P25 */
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0x1b, 0x0c, /* Set the BCLK,WCLK as output */
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0x1e, 0x80 + 28, /* Enable the BCLKN divider with value 28 */
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0x25, 0xee, /* DAC power up */
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0x12, 0x82, /* Power up the NADC divider with value 2 */
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0x13, 0x87, /* Power up the MADC divider with value 7 */
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0x14, 0x80, /* Program the OSR of ADC to 128 */
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0x3d, 0x01, /* Select ADC PRB_R1 */
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// Data routing
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0x00, 0x01, /* Select Page 1 */
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0x01, 0x08, /* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
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0x02, 0x01, /* Enable Master Analog Power Control */
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0x7b, 0x01, /* Set the REF charging time to 40ms */
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0x14, 0x25, /* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */
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0x0a, 0x33, /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */
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0x00, 0x01, // Select Page 1 */
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0x01, 0x08, // Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
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0x02, 0x01, // Enable Master Analog Power Control
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0x7b, 0x01, // Set the REF charging time to 40ms
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0x14, 0x25, // HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
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0x0a, 0x33, // Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V
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0x3d, 0x00, /* Select ADC PTM_R4 */
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0x47, 0x32, /* Set MicPGA startup delay to 6.4ms */
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0x7b, 0x01, /* Set the REF charging time to 40ms */
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0x34, REG_34_IN2L_TO_LEFT_P_10k, /* Route IN2L to LEFT_P with 10K */
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0x36, REG_36_IN2R_TO_LEFT_N_10k, /* Route IN2R to LEFT_N with 10K */
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//0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */
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//0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */
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//0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */
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//0x3c, 0x00, /* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */
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0x3d, 0x00, // Select ADC PTM_R4 */
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// 0x3d, 0xB6, // Select ADC PTM_R2 */
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0x47, 0x32, // Set MicPGA startup delay to 6.4ms
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0x7b, 0x01, // Set the REF charging time to 40ms
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0x34, REG_34_IN2L_TO_LEFT_P_10k, // Route IN2L to LEFT_P with 10K
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0x36, REG_36_IN2R_TO_LEFT_N_10k, // Route IN2R to LEFT_N with 10K
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//0x37, 0x04, // Route IN3R to RIGHT_P with 10K
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//0x39, 0x04, // Route IN3L to RIGHT_N with 10K
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//0x3b, 0x00, // Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB
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//0x3c, 0x00, // Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB
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};
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static const uint8_t conf_data_unmute[] = {
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// reg, data,
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0x00, 0x00, /* Select Page 0 */
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0x51, 0xc0, /* Power up Left and Right ADC Channels */
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0x52, 0x00, /* Unmute Left and Right ADC Digital Volume Control */
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0x00, 0x00, // Select Page 0
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0x51, 0xc0, // Power up Left and Right ADC Channels
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0x52, 0x00, // Unmute Left and Right ADC Digital Volume Control
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0x00, 0x01, // Select Page 1 (should be set as default)
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};
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static const uint8_t conf_data_ch3_select[] = {
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// reg, data,
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0x00, 0x01, /* Select Page 1 */
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0x37, REG_37_IN3R_TO_RIGHT_P_10k, /* Route IN3R to RIGHT_P with input impedance of 10K */
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0x39, REG_39_IN3L_TO_RIGHT_N_10k, /* Route IN3L to RIGHT_N with input impedance of 10K */
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//0x00, 0x01, // Select Page 1 (should be set as default)
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0x37, REG_37_IN3R_TO_RIGHT_P_10k, // Route IN3R to RIGHT_P with input impedance of 10K
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/*0x38,*/ 0x00, // Reserved
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/*0x39,*/ REG_39_IN3L_TO_RIGHT_N_10k, // Route IN3L to RIGHT_N with input impedance of 10K
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};
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static const uint8_t conf_data_ch1_select[] = {
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// reg, data,
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0x00, 0x01, /* Select Page 1 */
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0x37, REG_37_IN1R_TO_RIGHT_P_10k, /* Route IN1R to RIGHT_P with input impedance of 10K */
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0x39, REG_39_IN1L_TO_RIGHT_N_10k, /* Route IN1L to RIGHT_N with input impedance of 10K */
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//0x00, 0x01, // Select Page 1 (should be set as default)
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0x37, REG_37_IN1R_TO_RIGHT_P_10k, // Route IN1R to RIGHT_P with input impedance of 10K
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/*0x38,*/ 0x00, // Reserved
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/*0x39,*/ REG_39_IN1L_TO_RIGHT_N_10k, // Route IN1L to RIGHT_N with input impedance of 10K
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};
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static inline void
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static void
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tlv320aic3204_bulk_write(const uint8_t *buf, int len)
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{
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// i2cAcquireBus(&I2CD1);
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(void)i2cMasterTransmitTimeout(&I2CD1, AIC3204_ADDR, buf, len, NULL, 0, 1000);
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// i2cReleaseBus(&I2CD1);
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}
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#if 0
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@ -199,10 +245,10 @@ tlv320aic3204_read(uint8_t d0)
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static void
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tlv320aic3204_config(const uint8_t *data, int len)
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{
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i2cAcquireBus(&I2CD1);
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// i2cAcquireBus(&I2CD1);
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for (; len--; data += 2)
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tlv320aic3204_bulk_write(data, 2);
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i2cReleaseBus(&I2CD1);
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// i2cReleaseBus(&I2CD1);
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}
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void tlv320aic3204_init(void)
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@ -212,17 +258,35 @@ void tlv320aic3204_init(void)
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tlv320aic3204_config(conf_data_unmute, sizeof(conf_data_unmute)/2);
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}
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void tlv320aic3204_select(int channel)
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void
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tlv320aic3204_write_reg(uint8_t page, uint8_t reg, uint8_t data)
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{
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tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2);
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uint8_t buf[] = {
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0x00, page, // Select Page
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reg, data, // write reg data
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0x00, 0x01 // Select Page 1 (should be set as default)
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};
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tlv320aic3204_config(buf, sizeof(buf)/2);
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}
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void tlv320aic3204_set_gain(int lgain, int rgain)
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void tlv320aic3204_select(uint8_t channel)
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{
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// Cache current selected channel
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static uint8_t current_channel = -1;
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if (current_channel == channel)
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return;
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current_channel = channel;
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tlv320aic3204_bulk_write(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch1_select));
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// tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2);
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}
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void tlv320aic3204_set_gain(uint8_t lgain, uint8_t rgain)
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{
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uint8_t data[] = {
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0x00, 0x01, /* Select Page 1 */
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0x3b, lgain, /* Unmute Left MICPGA, set gain */
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0x3c, rgain, /* Unmute Right MICPGA, set gain */
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// 0x00, 0x01, // Select Page 1 (should be set as default)
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0x3b, lgain, // Unmute Left MICPGA, set gain
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/*0x3c,*/ rgain // Unmute Right MICPGA, set gain
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};
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tlv320aic3204_config(data, sizeof(data)/2);
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// tlv320aic3204_config(data, sizeof(data)/2);
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tlv320aic3204_bulk_write(data, sizeof(data));
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}
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3
ui.c
3
ui.c
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@ -934,8 +934,9 @@ const menuitem_t menu_transform[] = {
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};
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const menuitem_t menu_bandwidth[] = {
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{ MT_CALLBACK, BANDWIDTH_2000, "2 kHz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_1000, "1 kHz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_300, "300 Hz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_333, "333 Hz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_100, "100 Hz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_30, "30 Hz", menu_bandwidth_cb },
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{ MT_CALLBACK, BANDWIDTH_10, "10 Hz", menu_bandwidth_cb },
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