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Add support 96kHz ADC, allow increase sweep speed and bandwidth to 2kHz

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DiSlord 2020-04-29 14:34:05 +03:00
parent 23475a75c4
commit a1bbee724c
2 changed files with 126 additions and 61 deletions
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182
tlv320aic3204.c
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@ -20,7 +20,6 @@
#include "hal.h" #include "hal.h"
#include "nanovna.h" #include "nanovna.h"
#define REFCLK_8000KHZ
#define AIC3204_ADDR 0x18 #define AIC3204_ADDR 0x18
#define wait_ms(ms) chThdSleepMilliseconds(ms) #define wait_ms(ms) chThdSleepMilliseconds(ms)
@ -110,77 +109,124 @@
#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0) #define REG_39_CM2R_TO_RIGHT_N_40k (3<<0)
static const uint8_t conf_data[] = { static const uint8_t conf_data[] = {
// reg, data, // reg, data, // PLL clock config
// PLL clock config 0x00, 0x00, // Initialize to Page 0
0x00, 0x00, /* Initialize to Page 0 */ 0x01, 0x01, // Initialize the device through software reset
0x01, 0x01, /* Initialize the device through software reset */ 0x04, 0x03, // PLL Clock Low (80MHz - 137MHz), MCLK, PLL
0x04, 0x43, /* PLL Clock High, MCLK, PLL */ //=======================================================
#ifdef REFCLK_8000KHZ // Configure PLL clock
/* 8.000MHz*10.7520 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */ // PLL_CLKIN * R * J.D
0x05, 0x91, /* Power up PLL, P=1,R=1 */ // PLL_CLK = ---------------------
0x06, 0x0a, /* J=10 */ // P
0x07, 29, /* D=7520 = (29<<8) + 96 */ #if AUDIO_CLOCK_REF == 8000000U
0x08, 96, // 8.000MHz * 10.7520 = 86.016MHz,
0x05, 0x91, // Power up PLL, P=1,R=1
0x06, 0x0a, // J=10
0x07, 0x1D, // D=7520 = 0x1D60
0x08, 0x60,
#elif AUDIO_CLOCK_REF == 10752000U
// 10.752MHz * 4 * 2.0 / 1 = 86.016MHz
0x05, 0x94, // Power up PLL, P=1,R=4
0x06, 0x02, // J=2
0x07, 0x00, // D=0
0x08, 0x00,
#else
#error "Need set correct PLL multiplier for aic3204"
#endif #endif
// Configure ADC clock
// PLL_CLK
// ADC_fs = --------------------
// NADC * MADC * AOSR
#if AUDIO_ADC_FREQ == 48000
// Clock config, default fs=48kHz // Clock config, default fs=48kHz
0x0b, 0x82, /* Power up the NDAC divider with value 2 */ // from PLL 86.016MHz/(2*7*128) = 48kHz
0x0c, 0x87, /* Power up the MDAC divider with value 7 */ 0x0b, 0x82, // Power up the NDAC divider with value 2
0x0d, 0x00, /* Program the OSR of DAC to 128 */ 0x0c, 0x87, // Power up the MDAC divider with value 7
0x0e, 0x80, 0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 128
0x3c, 0x08, /* Set the DAC Mode to PRB_P8 */ 0x0e, 0x80, // DAC OSR Setting Register 2 (LSB)
//0x3c, 25, /* Set the DAC Mode to PRB_P25 */ 0x3c, 0x01, // Set the DAC Mode to PRB_P1
0x1b, 0x0c, /* Set the BCLK,WCLK as output */ 0x25, 0x00, // DAC power down
0x1e, 0x80 + 28, /* Enable the BCLKN divider with value 28 */
0x25, 0xee, /* DAC power up */ 0x12, 0x82, // Power up the NADC divider with value 2
0x13, 0x87, // Power up the MADC divider with value 7
0x14, 0x80, // ADC Oversampling (AOSR) Program the OSR of ADC to 128
0x3d, 0x01, // Select ADC PRB_R1
0x24, 0xee, // ADC power up
0x1b, 0x0c, // Set the BCLK,WCLK as output
0x1e, 0x80 + 28,// Enable the BCLKN divider with value 28 (I2S clock = 86.016MHz/(NDAC*28) = 48kHz * (16+16)
#elif AUDIO_ADC_FREQ == 96000
// Clock config, default fs=96kHz
// from PLL 86.016MHz/(2*7*64) = 96kHz
0x0b, 0x82, // Power up the NDAC divider with value 2
0x0c, 0x87, // Power up the MDAC divider with value 7
0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 64
0x0e, 0x40, // DAC OSR Setting Register 2 (LSB)
0x3c, 0x01, // Set the DAC Mode to PRB_P1
0x25, 0x00, // DAC power up
0x12, 0x82, // Power up the NADC divider with value 2
0x13, 0x87, // Power up the MADC divider with value 7
0x14, 0x40, // ADC Oversampling (AOSR) set OSR of ADC to 64
0x3d, 0x01, // Select ADC PRB_R1 (AOSR = 64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B))
0x24, 0xee, // ADC power up
0x1b, 0x0c, // Set the BCLK,WCLK as output
0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16)
#else
#error "Need set correct ADC clock for aic3204"
#endif
0x12, 0x82, /* Power up the NADC divider with value 2 */
0x13, 0x87, /* Power up the MADC divider with value 7 */
0x14, 0x80, /* Program the OSR of ADC to 128 */
0x3d, 0x01, /* Select ADC PRB_R1 */
// Data routing // Data routing
0x00, 0x01, /* Select Page 1 */ 0x00, 0x01, // Select Page 1 */
0x01, 0x08, /* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/ 0x01, 0x08, // Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
0x02, 0x01, /* Enable Master Analog Power Control */ 0x02, 0x01, // Enable Master Analog Power Control
0x7b, 0x01, /* Set the REF charging time to 40ms */ 0x7b, 0x01, // Set the REF charging time to 40ms
0x14, 0x25, /* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */ 0x14, 0x25, // HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
0x0a, 0x33, /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */ 0x0a, 0x33, // Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V
0x3d, 0x00, /* Select ADC PTM_R4 */ 0x3d, 0x00, // Select ADC PTM_R4 */
0x47, 0x32, /* Set MicPGA startup delay to 6.4ms */ // 0x3d, 0xB6, // Select ADC PTM_R2 */
0x7b, 0x01, /* Set the REF charging time to 40ms */ 0x47, 0x32, // Set MicPGA startup delay to 6.4ms
0x34, REG_34_IN2L_TO_LEFT_P_10k, /* Route IN2L to LEFT_P with 10K */ 0x7b, 0x01, // Set the REF charging time to 40ms
0x36, REG_36_IN2R_TO_LEFT_N_10k, /* Route IN2R to LEFT_N with 10K */ 0x34, REG_34_IN2L_TO_LEFT_P_10k, // Route IN2L to LEFT_P with 10K
//0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */ 0x36, REG_36_IN2R_TO_LEFT_N_10k, // Route IN2R to LEFT_N with 10K
//0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */ //0x37, 0x04, // Route IN3R to RIGHT_P with 10K
//0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */ //0x39, 0x04, // Route IN3L to RIGHT_N with 10K
//0x3c, 0x00, /* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */ //0x3b, 0x00, // Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB
//0x3c, 0x00, // Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB
}; };
static const uint8_t conf_data_unmute[] = { static const uint8_t conf_data_unmute[] = {
// reg, data, // reg, data,
0x00, 0x00, /* Select Page 0 */ 0x00, 0x00, // Select Page 0
0x51, 0xc0, /* Power up Left and Right ADC Channels */ 0x51, 0xc0, // Power up Left and Right ADC Channels
0x52, 0x00, /* Unmute Left and Right ADC Digital Volume Control */ 0x52, 0x00, // Unmute Left and Right ADC Digital Volume Control
0x00, 0x01, // Select Page 1 (should be set as default)
}; };
static const uint8_t conf_data_ch3_select[] = { static const uint8_t conf_data_ch3_select[] = {
// reg, data, // reg, data,
0x00, 0x01, /* Select Page 1 */ //0x00, 0x01, // Select Page 1 (should be set as default)
0x37, REG_37_IN3R_TO_RIGHT_P_10k, /* Route IN3R to RIGHT_P with input impedance of 10K */ 0x37, REG_37_IN3R_TO_RIGHT_P_10k, // Route IN3R to RIGHT_P with input impedance of 10K
0x39, REG_39_IN3L_TO_RIGHT_N_10k, /* Route IN3L to RIGHT_N with input impedance of 10K */ /*0x38,*/ 0x00, // Reserved
/*0x39,*/ REG_39_IN3L_TO_RIGHT_N_10k, // Route IN3L to RIGHT_N with input impedance of 10K
}; };
static const uint8_t conf_data_ch1_select[] = { static const uint8_t conf_data_ch1_select[] = {
// reg, data, // reg, data,
0x00, 0x01, /* Select Page 1 */ //0x00, 0x01, // Select Page 1 (should be set as default)
0x37, REG_37_IN1R_TO_RIGHT_P_10k, /* Route IN1R to RIGHT_P with input impedance of 10K */ 0x37, REG_37_IN1R_TO_RIGHT_P_10k, // Route IN1R to RIGHT_P with input impedance of 10K
0x39, REG_39_IN1L_TO_RIGHT_N_10k, /* Route IN1L to RIGHT_N with input impedance of 10K */ /*0x38,*/ 0x00, // Reserved
/*0x39,*/ REG_39_IN1L_TO_RIGHT_N_10k, // Route IN1L to RIGHT_N with input impedance of 10K
}; };
static inline void static void
tlv320aic3204_bulk_write(const uint8_t *buf, int len) tlv320aic3204_bulk_write(const uint8_t *buf, int len)
{ {
// i2cAcquireBus(&I2CD1);
(void)i2cMasterTransmitTimeout(&I2CD1, AIC3204_ADDR, buf, len, NULL, 0, 1000); (void)i2cMasterTransmitTimeout(&I2CD1, AIC3204_ADDR, buf, len, NULL, 0, 1000);
// i2cReleaseBus(&I2CD1);
} }
#if 0 #if 0
@ -199,10 +245,10 @@ tlv320aic3204_read(uint8_t d0)
static void static void
tlv320aic3204_config(const uint8_t *data, int len) tlv320aic3204_config(const uint8_t *data, int len)
{ {
i2cAcquireBus(&I2CD1); // i2cAcquireBus(&I2CD1);
for (; len--; data += 2) for (; len--; data += 2)
tlv320aic3204_bulk_write(data, 2); tlv320aic3204_bulk_write(data, 2);
i2cReleaseBus(&I2CD1); // i2cReleaseBus(&I2CD1);
} }
void tlv320aic3204_init(void) void tlv320aic3204_init(void)
@ -212,17 +258,35 @@ void tlv320aic3204_init(void)
tlv320aic3204_config(conf_data_unmute, sizeof(conf_data_unmute)/2); tlv320aic3204_config(conf_data_unmute, sizeof(conf_data_unmute)/2);
} }
void tlv320aic3204_select(int channel) void
tlv320aic3204_write_reg(uint8_t page, uint8_t reg, uint8_t data)
{ {
tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2); uint8_t buf[] = {
0x00, page, // Select Page
reg, data, // write reg data
0x00, 0x01 // Select Page 1 (should be set as default)
};
tlv320aic3204_config(buf, sizeof(buf)/2);
} }
void tlv320aic3204_set_gain(int lgain, int rgain) void tlv320aic3204_select(uint8_t channel)
{
// Cache current selected channel
static uint8_t current_channel = -1;
if (current_channel == channel)
return;
current_channel = channel;
tlv320aic3204_bulk_write(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch1_select));
// tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2);
}
void tlv320aic3204_set_gain(uint8_t lgain, uint8_t rgain)
{ {
uint8_t data[] = { uint8_t data[] = {
0x00, 0x01, /* Select Page 1 */ // 0x00, 0x01, // Select Page 1 (should be set as default)
0x3b, lgain, /* Unmute Left MICPGA, set gain */ 0x3b, lgain, // Unmute Left MICPGA, set gain
0x3c, rgain, /* Unmute Right MICPGA, set gain */ /*0x3c,*/ rgain // Unmute Right MICPGA, set gain
}; };
tlv320aic3204_config(data, sizeof(data)/2); // tlv320aic3204_config(data, sizeof(data)/2);
tlv320aic3204_bulk_write(data, sizeof(data));
} }

3
ui.c
View file

@ -934,8 +934,9 @@ const menuitem_t menu_transform[] = {
}; };
const menuitem_t menu_bandwidth[] = { const menuitem_t menu_bandwidth[] = {
{ MT_CALLBACK, BANDWIDTH_2000, "2 kHz", menu_bandwidth_cb },
{ MT_CALLBACK, BANDWIDTH_1000, "1 kHz", menu_bandwidth_cb }, { MT_CALLBACK, BANDWIDTH_1000, "1 kHz", menu_bandwidth_cb },
{ MT_CALLBACK, BANDWIDTH_300, "300 Hz", menu_bandwidth_cb }, { MT_CALLBACK, BANDWIDTH_333, "333 Hz", menu_bandwidth_cb },
{ MT_CALLBACK, BANDWIDTH_100, "100 Hz", menu_bandwidth_cb }, { MT_CALLBACK, BANDWIDTH_100, "100 Hz", menu_bandwidth_cb },
{ MT_CALLBACK, BANDWIDTH_30, "30 Hz", menu_bandwidth_cb }, { MT_CALLBACK, BANDWIDTH_30, "30 Hz", menu_bandwidth_cb },
{ MT_CALLBACK, BANDWIDTH_10, "10 Hz", menu_bandwidth_cb }, { MT_CALLBACK, BANDWIDTH_10, "10 Hz", menu_bandwidth_cb },