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add argument rdiv in si5351 setupMultisynth
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parent
c9e00287a3
commit
87858d5e5d
14
si5351.c
14
si5351.c
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@ -152,6 +152,7 @@ si5351_setupMultisynth(uint8_t output,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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uint32_t rdiv, // SI5351_R_DIV_1~128
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uint8_t drive_strength)
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{
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/* Get the appropriate starting point for the PLL registers */
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@ -203,7 +204,7 @@ si5351_setupMultisynth(uint8_t output,
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reg[0] = msreg_base[output];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = ((P1 & 0x00030000) >> 16) | div4;
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reg[3] = ((P1 & 0x00030000) >> 16) | div4 | rdiv;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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@ -251,7 +252,7 @@ si5351_set_frequency_fixedpll(int channel, int pll, int pllfreq, int freq,
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num >>= 1;
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denom >>= 1;
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}
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si5351_setupMultisynth(channel, pll, div, num, denom, drive_strength);
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si5351_setupMultisynth(channel, pll, div, num, denom, SI5351_R_DIV_1, drive_strength);
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}
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void
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@ -270,7 +271,7 @@ si5351_set_frequency_fixeddiv(int channel, int pll, int freq, int div,
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denom >>= 1;
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}
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si5351_setupPLL(pll, multi, num, denom);
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si5351_setupMultisynth(channel, pll, div, 0, 1, drive_strength);
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si5351_setupMultisynth(channel, pll, div, 0, 1, SI5351_R_DIV_1, drive_strength);
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}
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/*
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@ -336,6 +337,13 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
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break;
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case 1:
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// Set PLL twice on changing from band 2
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if (current_band == 2) {
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si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
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SI5351_CLK_DRIVE_STRENGTH_2MA);
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si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
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}
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// div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
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si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
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SI5351_CLK_DRIVE_STRENGTH_2MA);
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