commit 59020b8cfc7db0e2ebc0c5221dea1e1674c335f0 Author: TT Date: Mon Sep 5 07:27:44 2016 +0900 initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..9b52ada --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +*~ +.DS_Store +.dep +build diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..3a60ee1 --- /dev/null +++ b/Makefile @@ -0,0 +1,226 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../ChibiOS-RT +PROJ = . +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk +#include $(CHIBIOS)/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk +include NANOVNA_STM32_F072/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F072xB.ld + +CMSIS = CMSIS +DSPLIBINC = ${CMSIS}/Include +DSPLIBSRC = ${CMSIS}/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(STREAMSSRC) \ + $(SHELLSRC) \ + $(DSPLIBSRC) \ + usbcfg.c \ + main.c si5351.c si5351_low.c tlv320aic3204.c + +# $(TESTSRC) \ + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(DSPLIBINC) \ + $(STREAMSINC) $(SHELLINC) +# $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DSHELL_CMD_TEST_ENABLED=FALSE -DARM_MATH_CM0 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = -lm + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/NANOVNA_STM32_F072/board.c b/NANOVNA_STM32_F072/board.c new file mode 100644 index 0000000..bcf8f8a --- /dev/null +++ b/NANOVNA_STM32_F072/board.c @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +//extern void si5351_setup(void); + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + //si5351_setup(); + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/NANOVNA_STM32_F072/board.h b/NANOVNA_STM32_F072/board.h new file mode 100644 index 0000000..5c9e0e4 --- /dev/null +++ b/NANOVNA_STM32_F072/board.h @@ -0,0 +1,755 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Strawberry Linux STbee + */ + +/* + * Board identifier. + */ +#define BOARD_NANOVNA_STM32_F072 +#define BOARD_NAME "NanoVNA" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +#define STM32_HSE_BYPASS + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F072xB + +/* + * IO pins assignments + */ + +/* on-board */ + +#define GPIOA_BUTTON 0 +#define GPIOA_LEVER1 1 +#define GPIOA_LEVER2 2 +#define GPIOA_PUSH 3 +#define GPIOA_DAC2 5 +#define GPIOA_XP 6 +#define GPIOA_YP 7 +#define GPIOA_MCO 8 +#define GPIOA_USB_DISC 10 +#define GPIOA_USB_DM 11 +#define GPIOA_USB_DP 12 +#define GPIOA_JTMS 13 +#define GPIOA_JTCK 14 +#define GPIOA_LCD_RESET 15 + +#define GPIOB_XN 0 +#define GPIOB_YN 1 +#define GPIOB_SD_GP1 2 +#define GPIOB_SPI_SCLK 3 +#define GPIOB_SPI_MISO 4 +#define GPIOB_SPI_MOSI 5 +#define GPIOB_LCD_CS 6 +#define GPIOB_LCD_CD 7 +#define GPIOB_I2C1_SCL 8 +#define GPIOB_I2C1_SDA 9 +#define GPIOB_SD_GP2 10 +#define GPIOB_SD_CS 11 +#define GPIOB_I2S2_WCLK 12 +#define GPIOB_I2S2_BCLK 13 +#define GPIOB_I2S2_MOSI 15 + +#define GPIOC_LED 13 + +#define GPIOF_OSC_IN 0 +#define GPIOF_OSC_OUT 1 + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v##U) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA8 - MCO (alternate 0). + * PA11 - USB_DM (alternate 14). + * PA12 - USB_DP (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(0U) | \ + PIN_MODE_INPUT(1U) | \ + PIN_MODE_INPUT(2U) | \ + PIN_MODE_INPUT(3U) | \ + PIN_MODE_INPUT(4U) | \ + PIN_MODE_ANALOG(GPIOA_DAC2) | \ + PIN_MODE_ANALOG(GPIOA_XP) | \ + PIN_MODE_ANALOG(GPIOA_YP) | \ + PIN_MODE_ALTERNATE(GPIOA_MCO) | \ + PIN_MODE_INPUT(9U) | \ + PIN_MODE_OUTPUT(GPIOA_USB_DISC) | \ + PIN_MODE_INPUT(GPIOA_USB_DM) | \ + PIN_MODE_INPUT(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ + PIN_MODE_OUTPUT(GPIOA_LCD_RESET)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0U) | \ + PIN_OTYPE_PUSHPULL(1U) | \ + PIN_OTYPE_PUSHPULL(2U) | \ + PIN_OTYPE_PUSHPULL(3U) | \ + PIN_OTYPE_PUSHPULL(4U) | \ + PIN_OTYPE_PUSHPULL(5U) | \ + PIN_OTYPE_PUSHPULL(6U) | \ + PIN_OTYPE_PUSHPULL(7U) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MCO) | \ + PIN_OTYPE_PUSHPULL(9U) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DISC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_RESET)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(0) | \ + PIN_OSPEED_2M(1) | \ + PIN_OSPEED_2M(2) | \ + PIN_OSPEED_2M(3) | \ + PIN_OSPEED_2M(4) | \ + PIN_OSPEED_2M(5) | \ + PIN_OSPEED_2M(6) | \ + PIN_OSPEED_2M(7) | \ + PIN_OSPEED_100M(GPIOA_MCO) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(GPIOA_USB_DM) | \ + PIN_OSPEED_100M(GPIOA_USB_DP) | \ + PIN_OSPEED_100M(GPIOA_JTMS) | \ + PIN_OSPEED_100M(GPIOA_JTCK) | \ + PIN_OSPEED_100M(GPIOA_LCD_RESET)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLUP(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_PULLUP(GPIOA_MCO) | \ + PIN_PUPDR_PULLUP(9) | \ + PIN_PUPDR_PULLUP(GPIOA_USB_DISC) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTMS) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTCK) | \ + PIN_PUPDR_PULLDOWN(GPIOA_LCD_RESET)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(GPIOA_MCO) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(GPIOA_USB_DISC) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_JTMS) | \ + PIN_ODR_HIGH(GPIOA_JTCK) | \ + PIN_ODR_HIGH(GPIOA_LCD_RESET)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_MCO, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(GPIOA_USB_DISC, 0) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 0) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 0) | \ + PIN_AFIO_AF(GPIOA_JTMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTCK, 0) | \ + PIN_AFIO_AF(GPIOA_LCD_RESET, 0)) + +/* + * GPIOB setup: + * + * PB0 - XN analog + * PB1 - YN analog + * PB3 - SPI1_SCLK (alternate 0). + * PB4 - SPI1_MISO (alternate 0). + * PB5 - SPI1_MOSI (alternate 0). + * PB8 - I2C1_SCL (alternate 1). + * PB9 - I2C1_SDA (alternate 1). + * PB12 - I2S2_WCLK (alternate 0). + * PB13 - I2S2_BCLK (alternate 0). + * PB15 - I2S2_MOSI (alternate 0). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_XN) | \ + PIN_MODE_ANALOG(GPIOB_YN) | \ + PIN_MODE_OUTPUT(2) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI_SCLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI_MOSI) | \ + PIN_MODE_OUTPUT(6) | \ + PIN_MODE_OUTPUT(7) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_OUTPUT(10) | \ + PIN_MODE_OUTPUT(11) | \ + PIN_MODE_ALTERNATE(GPIOB_I2S2_WCLK) | \ + PIN_MODE_ALTERNATE(GPIOB_I2S2_BCLK) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(GPIOB_I2S2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2S2_WCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2S2_BCLK) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2S2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_PUPDR_FLOATING(GPIOB_XN) | \ + PIN_PUPDR_FLOATING(GPIOB_YN) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(GPIOB_I2S2_WCLK) | \ + PIN_OSPEED_100M(GPIOB_I2S2_BCLK) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(GPIOB_I2S2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(0) | \ + PIN_PUPDR_PULLUP(1) | \ + PIN_PUPDR_PULLUP(2) | \ + PIN_PUPDR_PULLUP(3) | \ + PIN_PUPDR_PULLUP(4) | \ + PIN_PUPDR_PULLUP(5) | \ + PIN_PUPDR_PULLUP(6) | \ + PIN_PUPDR_PULLUP(7) | \ + PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(10) | \ + PIN_PUPDR_PULLUP(11) | \ + PIN_PUPDR_PULLUP(GPIOB_I2S2_WCLK) | \ + PIN_PUPDR_PULLUP(GPIOB_I2S2_BCLK) | \ + PIN_PUPDR_PULLUP(14) | \ + PIN_PUPDR_PULLUP(GPIOB_I2S2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(GPIOB_I2S2_WCLK) | \ + PIN_ODR_HIGH(GPIOB_I2S2_BCLK) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(GPIOB_I2S2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(GPIOB_SPI_SCLK, 0) | \ + PIN_AFIO_AF(GPIOB_SPI_MOSI, 0) | \ + PIN_AFIO_AF(GPIOB_SPI_MISO, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 1) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 1) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(GPIOB_I2S2_WCLK, 0) | \ + PIN_AFIO_AF(GPIOB_I2S2_BCLK, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(GPIOB_I2S2_MOSI, 0)) +/* + * GPIOC setup: + * + * PC13 - LED (output pushpull maximum). + * PC14 - USB DISC (output pushpull maximum). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_OUTPUT(GPIOC_LED) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LED) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(GPIOC_LED) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(0) | \ + PIN_PUPDR_PULLUP(1) | \ + PIN_PUPDR_PULLUP(2) | \ + PIN_PUPDR_PULLUP(3) | \ + PIN_PUPDR_PULLUP(4) | \ + PIN_PUPDR_PULLUP(5) | \ + PIN_PUPDR_PULLUP(6) | \ + PIN_PUPDR_PULLUP(7) | \ + PIN_PUPDR_PULLUP(8) | \ + PIN_PUPDR_PULLUP(9) | \ + PIN_PUPDR_PULLUP(10) | \ + PIN_PUPDR_PULLUP(11) | \ + PIN_PUPDR_PULLUP(12) | \ + PIN_PUPDR_FLOATING(GPIOC_LED) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_PULLUP(15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(GPIOC_LED) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(GPIOC_LED, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOD setup: + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(0) | \ + PIN_PUPDR_PULLUP(1) | \ + PIN_PUPDR_PULLUP(2) | \ + PIN_PUPDR_PULLUP(3) | \ + PIN_PUPDR_PULLUP(4) | \ + PIN_PUPDR_PULLUP(5) | \ + PIN_PUPDR_PULLUP(6) | \ + PIN_PUPDR_PULLUP(7) | \ + PIN_PUPDR_PULLUP(8) | \ + PIN_PUPDR_PULLUP(9) | \ + PIN_PUPDR_PULLUP(10) | \ + PIN_PUPDR_PULLUP(11) | \ + PIN_PUPDR_PULLUP(12) | \ + PIN_PUPDR_PULLUP(13) | \ + PIN_PUPDR_PULLUP(14) | \ + PIN_PUPDR_PULLUP(15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input floating). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(0) | \ + PIN_PUPDR_PULLUP(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_PULLUP(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOF setup: + * + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/NANOVNA_STM32_F072/board.mk b/NANOVNA_STM32_F072/board.mk new file mode 100644 index 0000000..4b656e8 --- /dev/null +++ b/NANOVNA_STM32_F072/board.mk @@ -0,0 +1,7 @@ +# List of all the board related files. +#BOARDSRC = ${CHIBIOS}/os/hal/boards/NANOSDR_STM32_F303/board.c +BOARDSRC = ${PROJ}/NANOVNA_STM32_F072/board.c + +# Required include directories +#BOARDINC = ${CHIBIOS}/os/hal/boards/NANOSDR_STM32_F303 +BOARDINC = ${PROJ}/NANOVNA_STM32_F072 diff --git a/chconf.h b/chconf.h new file mode 100644 index 0000000..9ef2e7b --- /dev/null +++ b/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK TRUE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS TRUE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS TRUE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK TRUE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS TRUE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/ffconf.h b/ffconf.h new file mode 100644 index 0000000..ae0d38d --- /dev/null +++ b/ffconf.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1251 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 1 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/halconf.h b/halconf.h new file mode 100644 index 0000000..11c4000 --- /dev/null +++ b/halconf.h @@ -0,0 +1,377 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S TRUE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/main.c b/main.c new file mode 100644 index 0000000..c3ee45d --- /dev/null +++ b/main.c @@ -0,0 +1,378 @@ +#include "ch.h" +#include "hal.h" +#include "usbcfg.h" +#include "si5351.h" +#include "nanovna.h" + +#include +#include +#include +#include + +RTCDateTime timespec; + + +static const I2CConfig i2ccfg = { + 0x00902025, //voodoo magic + //0x00420F13, // 100kHz @ 72MHz + 0, + 0 +}; + +void I2CWrite(int addr, uint8_t d0, uint8_t d1) +{ + uint8_t buf[] = { d0, d1 }; + i2cAcquireBus(&I2CD1); + (void)i2cMasterTransmitTimeout(&I2CD1, addr, buf, 2, NULL, 0, 1000); + i2cReleaseBus(&I2CD1); +} + +int I2CRead(int addr, uint8_t d0) +{ + uint8_t buf[] = { d0 }; + i2cAcquireBus(&I2CD1); + i2cMasterTransmitTimeout(&I2CD1, addr, buf, 1, buf, 1, 1000); + i2cReleaseBus(&I2CD1); + return buf[0]; +} + +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) +{ + (void)arg; + + chRegSetThreadName("blink"); + + palSetPadMode(GPIOC, 13, PAL_MODE_OUTPUT_PUSHPULL); + while (1) + { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(GPIOC, 13); + chThdSleepMilliseconds(time); + palSetPad(GPIOC, 13); + chThdSleepMilliseconds(time); + } +} + +static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) +{ + (void)argc; + (void)argv; + + chprintf(chp, "Performing reset\r\n"); + + rccEnableWWDG(FALSE); + + WWDG->CFR = 0x60; + WWDG->CR = 0xff; + + while (1) + ; +} + +int32_t frequency_offset = 5000; +int32_t frequency = 10000000; + +void set_frequency(int freq) +{ + frequency = freq; + si5351_set_frequency(0, freq + frequency_offset); + si5351_set_frequency(1, freq); +} + +static void cmd_offset(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int freq; + if (argc != 1) { + chprintf(chp, "usage: offset {frequency offset(Hz)}\r\n"); + return; + } + frequency_offset = atoi(argv[0]); + set_frequency(frequency); +} + + +static void cmd_freq(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int freq; + if (argc != 1) { + chprintf(chp, "usage: freq {frequency(Hz)}\r\n"); + return; + } + freq = atoi(argv[0]); + set_frequency(freq); +} + +static void cmd_time(BaseSequentialStream *chp, int argc, char *argv[]) +{ + (void)argc; + (void)argv; + rtcGetTime(&RTCD1, ×pec); + chprintf(chp, "%d/%d/%d %d\r\n", timespec.year+1980, timespec.month, timespec.day, timespec.millisecond); +} + + +static const DACConfig dac1cfg1 = { + init: 2047U, + datamode: DAC_DHRM_12BIT_RIGHT +}; + +static void cmd_dac(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int value; + if (argc != 1) { + chprintf(chp, "usage: dac {value(0-4095)}\r\n"); + return; + } + value = atoi(argv[0]); +#if 1 + dacPutChannelX(&DACD2, 0, value); +#else + if (value & 1) + palSetPad(GPIOA, 5); + else + palClearPad(GPIOA, 5); +#endif +} + + + + +static struct { + int16_t rms[2]; + int16_t ave[2]; + int callback_count; + + int32_t last_counter_value; + int32_t interval_cycles; + int32_t busy_cycles; +} stat; + +int16_t rx_buffer[AUDIO_BUFFER_LEN * 2]; + +int16_t dump_buffer[AUDIO_BUFFER_LEN]; +volatile int16_t request_dump = 0; + + +void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n) +{ +#if PORT_SUPPORTS_RT + int32_t cnt_s = port_rt_get_counter_value(); + int32_t cnt_e; +#endif + int16_t *p = &rx_buffer[offset]; + uint32_t i; + (void)i2sp; + palSetPad(GPIOC, GPIOC_LED); + + if (request_dump > 0) { + if (request_dump == 1) + memcpy(dump_buffer, p, sizeof dump_buffer); + --request_dump; + } + //dsp_process(p, n); + +#if PORT_SUPPORTS_RT + cnt_e = port_rt_get_counter_value(); + stat.interval_cycles = cnt_s - stat.last_counter_value; + stat.busy_cycles = cnt_e - cnt_s; + stat.last_counter_value = cnt_s; +#endif + stat.callback_count++; + palClearPad(GPIOC, GPIOC_LED); +} + +static const I2SConfig i2sconfig = { + NULL, // TX Buffer + rx_buffer, // RX Buffer + AUDIO_BUFFER_LEN * 2, + NULL, // tx callback + i2s_end_callback, // rx callback + 0, // i2scfgr + 2 // i2spr +}; + +static void cmd_data(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int i, j; + (void)argc; + (void)argv; + +#if 0 + int16_t *buf = rx_buffer; + i2sStopExchange(&I2SD2); + for (i = 0; i < AUDIO_BUFFER_LEN; ) { + for (j = 0; j < 16; j++, i++) { + chprintf(chp, "%04x ", 0xffff & (int)buf[i]); + } + chprintf(chp, "\r\n"); + } + i2sStartExchange(&I2SD2); +#else + int16_t *buf = dump_buffer; + request_dump = 3; + while (request_dump) + ; + for (i = 0; i < AUDIO_BUFFER_LEN; ) { + for (j = 0; j < 16; j++, i++) { + chprintf(chp, "%04x ", 0xffff & (int)buf[i]); + } + chprintf(chp, "\r\n"); + } +#endif +} + +static void cmd_gain(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int rvalue; + int lvalue = 0; + if (argc != 1 && argc != 2) { + chprintf(chp, "usage: gain {lgain(0-95)} [rgain(0-95)]\r\n"); + return; + } + rvalue = atoi(argv[0]); + if (argc == 2) + lvalue = atoi(argv[1]); + tlv320aic3204_set_gain(lvalue, rvalue); +} + +static void cmd_port(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int port; + if (argc != 1) { + chprintf(chp, "usage: port {0:TX 1:RX}\r\n"); + return; + } + port = atoi(argv[0]); + if (port) + tlv320aic3204_select_in1(); + else + tlv320aic3204_select_in3(); // default +} + +static void cmd_stat(BaseSequentialStream *chp, int argc, char *argv[]) +{ + int16_t *p = &rx_buffer[0]; + int32_t acc0, acc1; + int32_t ave0, ave1; + int32_t count = AUDIO_BUFFER_LEN; + int i; + (void)argc; + (void)argv; + acc0 = acc1 = 0; + for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { + acc0 += p[i]; + acc1 += p[i+1]; + } + ave0 = acc0 / count; + ave1 = acc1 / count; + acc0 = acc1 = 0; + for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { + acc0 += (p[i] - ave0)*(p[i] - ave0); + acc1 += (p[i+1] - ave1)*(p[i+1] - ave1); + } + stat.rms[0] = sqrt(acc0 / count); + stat.rms[1] = sqrt(acc1 / count); + stat.ave[0] = ave0; + stat.ave[1] = ave1; + + chprintf(chp, "average: %d %d\r\n", stat.ave[0], stat.ave[1]); + chprintf(chp, "rms: %d %d\r\n", stat.rms[0], stat.rms[1]); + chprintf(chp, "callback count: %d\r\n", stat.callback_count); + chprintf(chp, "interval cycle: %d\r\n", stat.interval_cycles); + chprintf(chp, "busy cycle: %d\r\n", stat.busy_cycles); + chprintf(chp, "load: %d\r\n", stat.busy_cycles * 100 / stat.interval_cycles); +} + + + + + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static const ShellCommand commands[] = +{ + { "reset", cmd_reset }, + { "freq", cmd_freq }, + { "offset", cmd_offset }, + { "time", cmd_time }, + { "dac", cmd_dac }, + { "data", cmd_data }, + { "port", cmd_port }, + { "stat", cmd_stat }, + { "gain", cmd_gain }, + { NULL, NULL } +}; + +static const ShellConfig shell_cfg1 = +{ + (BaseSequentialStream *)&SDU1, + commands +}; + +int main(void) +{ + halInit(); + chSysInit(); + + /* + * Starting DAC1 driver, setting up the output pin as analog as suggested + * by the Reference Manual. + */ + //palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG); + //palSetPadMode(GPIOA, 5, PAL_MODE_OUTPUT_PUSHPULL); + //palSetPadMode(GPIOA, 5, PAL_MODE_INPUT); + dacStart(&DACD2, &dac1cfg1); + + //palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN); + //palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN); + i2cStart(&I2CD1, &i2ccfg); + si5351_init(); + + // MCO on PA8 + //palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(0)); + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(100); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * I2S Initialize + */ + tlv320aic3204_init(); + i2sInit(); + i2sObjectInit(&I2SD2); + i2sStart(&I2SD2, &i2sconfig); + i2sStartExchange(&I2SD2); + + /* + * Shell manager initialization. + */ + shellInit(); + + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + set_frequency(10000000); + + while (1) + { + if (SDU1.config->usbp->state == USB_ACTIVE) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/mcuconf.h b/mcuconf.h new file mode 100644 index 0000000..d061767 --- /dev/null +++ b/mcuconf.h @@ -0,0 +1,223 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 +#define STM32_GPT_TIM14_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 +#define STM32_I2C_USE_DMA TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI1 FALSE +#define STM32_I2S_USE_SPI2 TRUE +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI1_IRQ_PRIORITY 2 +#define STM32_I2S_SPI2_IRQ_PRIORITY 2 +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/nanovna.h b/nanovna.h new file mode 100644 index 0000000..b3d88ff --- /dev/null +++ b/nanovna.h @@ -0,0 +1,33 @@ + +extern void I2CWrite(int addr, uint8_t d0, uint8_t d1); + +typedef struct { + int target_level; + int gain_hysteresis; + int attack; + int attack_scale; + int decay; + int decay_scale; +} tlv320aic3204_agc_config_t; + +extern void tlv320aic3204_init(void); +extern void tlv320aic3204_set_gain(int lgain, int rgain); +extern void tlv320aic3204_set_digital_gain(int gain); +extern void tlv320aic3204_set_volume(int gain); +extern void tlv320aic3204_agc_config(tlv320aic3204_agc_config_t *conf); + +extern void ui_init(void); +extern void ui_process(void); + +// 5ms @ 48kHz +#define AUDIO_BUFFER_LEN 480 + +extern int16_t rx_buffer[]; +extern int16_t tx_buffer[]; + +extern int16_t buffer_i[]; +extern int16_t buffer_q[]; + +void dsp_process(int16_t *src, int16_t *dst, size_t len); +void set_agc_mode(int agcmode); + diff --git a/prog.sh b/prog.sh new file mode 100755 index 0000000..e9454be --- /dev/null +++ b/prog.sh @@ -0,0 +1,3 @@ +#! /bin/sh +DFU_UTIL=../chibios-stm/dfu-util/src/dfu-util +$DFU_UTIL -d 0483:df11 -a 0 -s 0x08000000:leave -D build/ch.bin diff --git a/si5351.c b/si5351.c new file mode 100644 index 0000000..ce5f396 --- /dev/null +++ b/si5351.c @@ -0,0 +1,210 @@ +#include "hal.h" +#include "si5351.h" + +#define SI5351_I2C_ADDR (0x60<<1) + +extern int I2CWrite(int addr, char d0, char d1); + +static void +si5351_write(uint8_t reg, uint8_t dat) +{ + int addr = SI5351_I2C_ADDR>>1; + uint8_t buf[] = { reg, dat }; + i2cAcquireBus(&I2CD1); + (void)i2cMasterTransmitTimeout(&I2CD1, addr, buf, 2, NULL, 0, 1000); + i2cReleaseBus(&I2CD1); +} + +static void +si5351_bulk_write(const uint8_t *buf, int len) +{ + int addr = SI5351_I2C_ADDR>>1; + i2cAcquireBus(&I2CD1); + (void)i2cMasterTransmitTimeout(&I2CD1, addr, buf, len, NULL, 0, 1000); + i2cReleaseBus(&I2CD1); +} + +// register addr, length, data, ... +const uint8_t si5351_configs[] = { + 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff, + 4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, + 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF, + // setup PLL (26MHz * 32 = 832MHz, 32/2-2=14) + 9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0, + // RESET PLL + 2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B, + // setup multisynth (832MHz / 104 = 8MHz, 104/2-2=50) + 9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0, + 2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE, + 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0, + 0 // sentinel +}; + +void +si5351_init(void) +{ + const uint8_t *p = si5351_configs; + while (*p) { + uint8_t len = *p++; + si5351_bulk_write(p, len); + p += len; + } +} + +void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */ + uint8_t mult, + uint32_t num, + uint32_t denom) +{ + /* Get the appropriate starting point for the PLL registers */ + const uint8_t pllreg_base[] = { + SI5351_REG_26_PLL_A, + SI5351_REG_34_PLL_B + }; + uint8_t baseaddr = pllreg_base[pll]; + + uint32_t P1; + uint32_t P2; + uint32_t P3; + + /* Feedback Multisynth Divider Equation + * where: a = mult, b = num and c = denom + * P1 register is an 18-bit value using following formula: + * P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512 + * P2 register is a 20-bit value using the following formula: + * P2[19:0] = 128 * num - denom * floor(128*(num/denom)) + * P3 register is a 20-bit value using the following formula: + * P3[19:0] = denom + */ + + /* Set the main PLL config registers */ + if (num == 0) + { + /* Integer mode */ + P1 = 128 * mult - 512; + P2 = num; + P3 = denom; + } + else + { + /* Fractional mode */ + //P1 = (uint32_t)(128 * mult + floor(128 * ((float)num/(float)denom)) - 512); + P1 = 128 * mult + ((128 * num) / denom) - 512; + //P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + P2 = 128 * num - denom * ((128 * num) / denom); + P3 = denom; + } + + /* The datasheet is a nightmare of typos and inconsistencies here! */ + si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8); + si5351_write(baseaddr+1, (P3 & 0x000000FF)); + si5351_write(baseaddr+2, (P1 & 0x00030000) >> 16); + si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8); + si5351_write(baseaddr+4, (P1 & 0x000000FF)); + si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ); + si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8); + si5351_write(baseaddr+7, (P2 & 0x000000FF)); + + /* Reset both PLLs */ + si5351_write(SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); +} + +void +si5351_setupMultisynth(uint8_t output, + uint8_t pllSource, + uint32_t div, // 4,6,8, 8+ ~ 900 + uint32_t num, + uint32_t denom) +{ + /* Get the appropriate starting point for the PLL registers */ + const uint8_t msreg_base[] = { + SI5351_REG_42_MULTISYNTH0, + SI5351_REG_50_MULTISYNTH1, + SI5351_REG_58_MULTISYNTH2, + }; + uint8_t baseaddr = msreg_base[output]; + const uint8_t clkctrl[] = { + SI5351_REG_16_CLK0_CONTROL, + SI5351_REG_17_CLK1_CONTROL, + SI5351_REG_18_CLK2_CONTROL + }; + uint8_t dat; + + uint32_t P1; + uint32_t P2; + uint32_t P3; + + /* Output Multisynth Divider Equations + * where: a = div, b = num and c = denom + * P1 register is an 18-bit value using following formula: + * P1[17:0] = 128 * a + floor(128*(b/c)) - 512 + * P2 register is a 20-bit value using the following formula: + * P2[19:0] = 128 * b - c * floor(128*(b/c)) + * P3 register is a 20-bit value using the following formula: + * P3[19:0] = c + */ + /* Set the main PLL config registers */ + if (num == 0) + { + /* Integer mode */ + P1 = 128 * div - 512; + P2 = num; + P3 = denom; + } + else + { + /* Fractional mode */ + //P1 = (uint32_t)(128 * div + floor(128 * ((float)num/(float)denom)) - 512); + P1 = 128 * div + ((128 * num) / denom) - 512; + //P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + P2 = 128 * num - denom * ((128 * num) / denom); + P3 = denom; + } + + /* Set the MSx config registers */ + si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8); + si5351_write(baseaddr+1, (P3 & 0x000000FF)); + si5351_write(baseaddr+2, (P1 & 0x00030000) >> 16); /* ToDo: Add DIVBY4 (>150MHz) and R0 support (<500kHz) later */ + si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8); + si5351_write(baseaddr+4, (P1 & 0x000000FF)); + si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16)); + si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8); + si5351_write(baseaddr+7, (P2 & 0x000000FF)); + + /* Configure the clk control and enable the output */ + dat = SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N; + if (pllSource == SI5351_PLL_B) + dat |= SI5351_CLK_PLL_SELECT_B; + if (num == 0) + dat |= SI5351_CLK_INTEGER_MODE; + si5351_write(clkctrl[output], dat); +} + +//#define PLLFREQ 800000000L + +void +si5351_set_frequency(int channel, int freq) +{ +#if 0 +#define PLLFREQ (26000000L * 32) + int32_t div = PLLFREQ / freq; // 6 ~ 1800 + int32_t num = PLLFREQ - freq * div; + int32_t denom = freq; + int32_t k = freq / (1<<20) + 1; + num /= k; + denom /= k; + si5351_setupMultisynth(channel, SI5351_PLL_A, div, num, denom); +#else +#define PLLFREQ (26000000L * 40) + int32_t div = PLLFREQ / freq; // 8 ~ 1800 + int32_t num = PLLFREQ - freq * div; + int32_t denom = freq; + int32_t k = freq / (1<<20) + 1; + num /= k; + denom /= k; + si5351_setupPLL(SI5351_PLL_B, 40, 0, 1); + si5351_setupMultisynth(channel, SI5351_PLL_B, div, num, denom); +#endif +} + + diff --git a/si5351.h b/si5351.h new file mode 100644 index 0000000..37cd61c --- /dev/null +++ b/si5351.h @@ -0,0 +1,67 @@ +#define SI5351_PLL_A 0 +#define SI5351_PLL_B 1 + +#define SI5351_MULTISYNTH_DIV_4 4 +#define SI5351_MULTISYNTH_DIV_6 6 +#define SI5351_MULTISYNTH_DIV_8 8 +#define SI5351_R_DIV_1 0 +#define SI5351_R_DIV_2 1 +#define SI5351_R_DIV_4 2 +#define SI5351_R_DIV_8 3 +#define SI5351_R_DIV_16 4 +#define SI5351_R_DIV_32 5 +#define SI5351_R_DIV_64 6 +#define SI5351_R_DIV_128 7 + +#define SI5351_REG_3_OUTPUT_ENABLE_CONTROL 3 +#define SI5351_REG_16_CLK0_CONTROL 16 +#define SI5351_REG_17_CLK1_CONTROL 17 +#define SI5351_REG_18_CLK2_CONTROL 18 +#define SI5351_REG_26_PLL_A 26 +#define SI5351_REG_34_PLL_B 34 +#define SI5351_REG_42_MULTISYNTH0 42 +#define SI5351_REG_50_MULTISYNTH1 50 +#define SI5351_REG_58_MULTISYNTH2 58 + +#define SI5351_CLK_POWERDOWN (1<<7) +#define SI5351_CLK_INTEGER_MODE (1<<6) +#define SI5351_CLK_PLL_SELECT_B (1<<5) +#define SI5351_CLK_INVERT (1<<4) + +#define SI5351_CLK_INPUT_MASK (3<<2) +#define SI5351_CLK_INPUT_XTAL (0<<2) +#define SI5351_CLK_INPUT_CLKIN (1<<2) +#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2) +#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2) + +#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0) +#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0) +#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0) +#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0) +#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0) + + +#define SI5351_REG_177_PLL_RESET 177 +#define SI5351_PLL_RESET_B (1<<7) +#define SI5351_PLL_RESET_A (1<<5) + +#define SI5351_REG_183_CRYSTAL_LOAD 183 +#define SI5351_CRYSTAL_LOAD_6PF (1<<6) +#define SI5351_CRYSTAL_LOAD_8PF (2<<6) +#define SI5351_CRYSTAL_LOAD_10PF (3<<6) + +#define SI5351_CRYSTAL_FREQ_25MHZ 25000000 + +void si5351_init(void); + +void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */ + uint8_t mult, + uint32_t num, + uint32_t denom); +void si5351_setupMultisynth(uint8_t output, + uint8_t pllSource, + uint32_t div, + uint32_t num, + uint32_t denom); + +void si5351_set_frequency(int channel, int freq); diff --git a/si5351_low.c b/si5351_low.c new file mode 100644 index 0000000..37a6a1b --- /dev/null +++ b/si5351_low.c @@ -0,0 +1,109 @@ +#include "hal.h" +#include "si5351.h" + +#define SI5351_I2C_ADDR (0x60<<1) + +static void +rcc_gpio_init(void) +{ + // Reset AHB,APB1,APB2 + RCC->AHBRSTR |= 0xffffffff; + RCC->AHBRSTR = 0; + RCC->APB1RSTR |= 0xffffffff; + RCC->APB1RSTR = 0; + RCC->APB2RSTR |= 0xffffffff; + RCC->APB2RSTR = 0; + + RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_I2C1EN; + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + RCC->CFGR3 |= RCC_CFGR3_I2C1SW_HSI; + + // STM32F072 + GPIOB->AFRH = 0x55550011; // PB8,PB9 Alternate Function 1 + // STM32F303 + //GPIOB->AFRH = 0x55550044; // PB8,PB9 Alternate Function 4 + GPIOB->OTYPER |= 0x0300; // PB8,PB9 Open drain + GPIOB->MODER |= 0x000A0000;// + GPIOB->OSPEEDR |= 0x00050000;// +} + +static void +i2c_init(I2C_TypeDef* i2c) +{ + // Disable the I2Cx peripheral + i2c->CR1 &= ~I2C_CR1_PE; + while (i2c->CR1 & I2C_CR1_PE); + + // 100kHz @ 8MHz + i2c->TIMINGR = 0x10420F13; + + // Use 7-bit addresses + i2c->CR2 &=~ I2C_CR2_ADD10; + + // Enable the analog filter + i2c->CR1 &= ~I2C_CR1_ANFOFF; + + // Disable NOSTRETCH + i2c->CR1 |= I2C_CR1_NOSTRETCH; + + // Enable I2Cx peripheral clock. + // Select APB1 as clock source + if (i2c == I2C1) { + RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; + } else if (i2c == I2C2) { + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; + } + + // Enable the I2Cx peripheral + i2c->CR1 |= I2C_CR1_PE; +} + +static void +i2cSendByte(I2C_TypeDef* i2c, uint8_t addr, const uint8_t *buf, uint8_t len) +{ + i2c->CR2 = (I2C_CR2_SADD & addr) // Set the slave address + | (I2C_CR2_NBYTES & (len << 16)) // Send one byte + | I2C_CR2_START // Generate start condition + | I2C_CR2_AUTOEND; // Generate stop condition after sent + + // Send the data + while (len-- > 0) { + while (!(i2c->ISR & I2C_ISR_TXIS)); + i2c->TXDR = (I2C_TXDR_TXDATA & *buf++); + } +} + +// register addr, length, data, ... +const uint8_t si5351_configs_low[] = { + 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff, + 4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, + 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF, + // setup PLL (26MHz * 32 = 832MHz : 32/2-2=14) + 9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0, + // RESET PLL + 2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B, + // setup multisynth (832MHz/8MHz=104,104/2-2=50) + 9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0, + 2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE, + 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0, + 0 // sentinel +}; + +void +si5351_init_bulk(void) +{ + const uint8_t *p = si5351_configs_low; + while (*p) { + uint8_t len = *p++; + i2cSendByte(I2C1, SI5351_I2C_ADDR, p, len); + p += len; + } +} + +void +si5351_setup(void) +{ + rcc_gpio_init(); + i2c_init(I2C1); + si5351_init_bulk(); +} diff --git a/tlv320aic3204.c b/tlv320aic3204.c new file mode 100644 index 0000000..df2ff1a --- /dev/null +++ b/tlv320aic3204.c @@ -0,0 +1,157 @@ +#include "hal.h" +#include "nanovna.h" + + +#define REFCLK_8000KHZ +#define AIC3204_ADDR 0x18 + +#define wait_ms(ms) chThdSleepMilliseconds(ms) + + +void tlv320aic3204_init(void) +{ + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Initialize to Page 0 */ + I2CWrite(AIC3204_ADDR, 0x01, 0x01); /* Initialize the device through software reset */ + I2CWrite(AIC3204_ADDR, 0x04, 0x43); /* PLL Clock High, MCLK, PLL */ +#ifdef REFCLK_8000KHZ + /* 8.000MHz*10.7520 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */ + I2CWrite(AIC3204_ADDR, 0x05, 0x91); /* Power up PLL, P=1,R=1 */ + I2CWrite(AIC3204_ADDR, 0x06, 0x0a); /* J=10 */ + I2CWrite(AIC3204_ADDR, 0x07, 29); /* D=7520 = (29<<8) + 96 */ + I2CWrite(AIC3204_ADDR, 0x08, 96); +#endif +#ifdef REFCLK_12000KHZ + /* 12.000MHz*7.1680 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */ + I2CWrite(AIC3204_ADDR, 0x05, 0x91); /* Power up PLL, P=1,R=1 */ + I2CWrite(AIC3204_ADDR, 0x06, 0x07); /* J=7 */ + I2CWrite(AIC3204_ADDR, 0x07, 6); /* D=1680 = (6<<8) + 144 */ + I2CWrite(AIC3204_ADDR, 0x08, 144); +#endif +#ifdef REFCLK_19200KHZ + /* 19.200MHz*4.48 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */ + I2CWrite(AIC3204_ADDR, 0x05, 0x91); /* Power up PLL, P=1,R=1 */ + I2CWrite(AIC3204_ADDR, 0x06, 0x04); /* J=4 */ + I2CWrite(AIC3204_ADDR, 0x07, 18); /* D=4800 = (18<<8) + 192 */ + I2CWrite(AIC3204_ADDR, 0x08, 192); +#endif + I2CWrite(AIC3204_ADDR, 0x0b, 0x82); /* Power up the NDAC divider with value 2 */ + I2CWrite(AIC3204_ADDR, 0x0c, 0x87); /* Power up the MDAC divider with value 7 */ + I2CWrite(AIC3204_ADDR, 0x0d, 0x00); /* Program the OSR of DAC to 128 */ + I2CWrite(AIC3204_ADDR, 0x0e, 0x80); + I2CWrite(AIC3204_ADDR, 0x3c, 0x08); /* Set the DAC Mode to PRB_P8 */ + I2CWrite(AIC3204_ADDR, 0x1b, 0x0c); /* Set the BCLK,WCLK as output */ + I2CWrite(AIC3204_ADDR, 0x1e, 0x80 + 28); /* Enable the BCLKN divider with value 28 */ + I2CWrite(AIC3204_ADDR, 0x25, 0xee); /* DAC power up */ + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x01, 0x08); /* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/ + I2CWrite(AIC3204_ADDR, 0x02, 0x01); /* Enable Master Analog Power Control */ + I2CWrite(AIC3204_ADDR, 0x7b, 0x01); /* Set the REF charging time to 40ms */ +// I2CWrite(AIC3204_ADDR, 0x0a, 0x00); /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to Input Common Mode */ + I2CWrite(AIC3204_ADDR, 0x0a, 0x33); /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */ + + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ + I2CWrite(AIC3204_ADDR, 0x12, 0x87); /* Power up the NADC divider with value 7 */ + I2CWrite(AIC3204_ADDR, 0x13, 0x82); /* Power up the MADC divider with value 2 */ + I2CWrite(AIC3204_ADDR, 0x14, 0x80); /* Program the OSR of ADC to 128 */ + I2CWrite(AIC3204_ADDR, 0x3d, 0x01); /* Select ADC PRB_R1 */ + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x3d, 0x00); /* Select ADC PTM_R4 */ + I2CWrite(AIC3204_ADDR, 0x47, 0x32); /* Set MicPGA startup delay to 3.1ms */ + I2CWrite(AIC3204_ADDR, 0x7b, 0x01); /* Set the REF charging time to 40ms */ + I2CWrite(AIC3204_ADDR, 0x34, 0x10); /* Route IN2L to LEFT_P with 10K input impedance */ + I2CWrite(AIC3204_ADDR, 0x36, 0x10); /* Route IN2R to LEFT_N with 10K input impedance */ + I2CWrite(AIC3204_ADDR, 0x37, 0x04); /* Route IN3R to RIGHT_P with input impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x39, 0x04); /* Route IN3L to RIGHT_N with impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x3b, 0); /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */ + I2CWrite(AIC3204_ADDR, 0x3c, 0); /* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */ + + wait_ms(40); + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ + I2CWrite(AIC3204_ADDR, 0x51, 0xc0); /* Power up Left and Right ADC Channels */ + I2CWrite(AIC3204_ADDR, 0x52, 0x00); /* Unmute Left and Right ADC Digital Volume Control */ +} + +void tlv320aic3204_select_in3(void) +{ + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x37, 0x04); /* Route IN3R to RIGHT_P with input impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x39, 0x04); /* Route IN3L to RIGHT_N with input impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ +} + +void tlv320aic3204_select_in1(void) +{ + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x37, 0x40); /* Route IN1R to RIGHT_P with input impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x39, 0x10); /* Route IN1L to RIGHT_N with input impedance of 10K */ + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ +} + +void tlv320aic3204_set_gain(int lgain, int rgain) +{ + if (lgain < 0) + lgain = 0; + if (lgain > 95) + lgain = 95; + if (rgain < 0) + rgain = 0; + if (rgain > 95) + rgain = 95; + + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x3b, lgain); /* Unmute Left MICPGA, set gain */ + I2CWrite(AIC3204_ADDR, 0x3c, rgain); /* Unmute Right MICPGA, set gain */ + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ +} + +void tlv320aic3204_set_digital_gain(int gain) +{ + if (gain < -24) + gain = -24; + if (gain > 40) + gain = 40; + + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ + I2CWrite(AIC3204_ADDR, 0x53, gain & 0x7f); /* Left ADC Channel Volume */ + I2CWrite(AIC3204_ADDR, 0x54, gain & 0x7f); /* Right ADC Channel Volume */ +} + +void tlv320aic3204_set_volume(int gain) +{ + if (gain > 29) + gain = 29; + else if (gain < -6) + gain = 0x40; + else + gain &= 0x3f; + + I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */ + I2CWrite(AIC3204_ADDR, 0x10, gain); /* Unmute Left MICPGA, set gain */ + I2CWrite(AIC3204_ADDR, 0x11, gain); /* Unmute Right MICPGA, set gain */ + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ +} + +void tlv320aic3204_agc_config(tlv320aic3204_agc_config_t *conf) +{ + int ctrl = 0; + if (conf == NULL) { + ctrl = 0; + } else { + ctrl = 0x80 + | ((conf->target_level & 0x7) << 4) + | (conf->gain_hysteresis & 0x3); + } + I2CWrite(AIC3204_ADDR, 0x00, 0x00); /* Select Page 0 */ + I2CWrite(AIC3204_ADDR, 0x56, ctrl); /* Left AGC Control Register */ + I2CWrite(AIC3204_ADDR, 0x5e, ctrl); /* Right AGC Control Register */ + if (ctrl == 0) + return; + + ctrl = ((conf->attack & 0x1f) << 3) | (conf->attack_scale & 0x7); + I2CWrite(AIC3204_ADDR, 0x59, ctrl); /* Left AGC Attack Time */ + I2CWrite(AIC3204_ADDR, 0x61, ctrl); /* Right AGC Attack Time */ + + ctrl = ((conf->decay & 0x1f) << 3) | (conf->decay_scale & 0x7); + I2CWrite(AIC3204_ADDR, 0x5a, ctrl); /* Left AGC Decay Time */ + I2CWrite(AIC3204_ADDR, 0x62, ctrl); /* Right AGC Decay Time */ +} diff --git a/usbcfg.c b/usbcfg.c new file mode 100644 index 0000000..07a4927 --- /dev/null +++ b/usbcfg.c @@ -0,0 +1,334 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduDisconnectI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/usbcfg.h b/usbcfg.h new file mode 100644 index 0000000..2da1c40 --- /dev/null +++ b/usbcfg.h @@ -0,0 +1,26 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _USBCFG_H_ +#define _USBCFG_H_ + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* _USBCFG_H_ */ + +/** @} */