diff --git a/main.c b/main.c
index 96648e7..e52ac7f 100644
--- a/main.c
+++ b/main.c
@@ -132,12 +132,20 @@ int set_frequency(int freq)
     if (frequency == freq)
       return delay;
 
-    if (freq > 900000000 && frequency <= 900000000) {
+    if (freq > 1400000000 && frequency <= 1400000000) {
       tlv320aic3204_set_gain(95, 95);
       delay += 10;
     } else
+    if (freq > 1200000000 && frequency <= 1200000000) {
+      tlv320aic3204_set_gain(85, 85);
+      delay += 10;
+    } else
+    if (freq > 900000000 && frequency <= 900000000) {
+      tlv320aic3204_set_gain(75, 75);
+      delay += 10;
+    } else
     if (freq > 600000000 && frequency <= 600000000) {
-      tlv320aic3204_set_gain(60, 60);
+      tlv320aic3204_set_gain(50, 50);
       delay += 10;
     } else
     if (freq > FREQ_HARMONICS && frequency <= FREQ_HARMONICS) {
diff --git a/si5351.c b/si5351.c
index 6590493..ebd4aa9 100644
--- a/si5351.c
+++ b/si5351.c
@@ -352,7 +352,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
     }
 
     si5351_set_frequency_fixedpll(0, SI5351_PLL_A, PLLFREQ, ofreq,
-                                  rdiv, SI5351_CLK_DRIVE_STRENGTH_2MA);
+                                  rdiv, drive_strength);
     si5351_set_frequency_fixedpll(1, SI5351_PLL_A, PLLFREQ, freq,
                                   rdiv, drive_strength);
     //if (current_band != 0)
@@ -363,14 +363,12 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
   case 1:
     // Set PLL twice on changing from band 2
     if (current_band == 2) {
-      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
-                                    SI5351_CLK_DRIVE_STRENGTH_2MA);
+      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6, drive_strength);
       si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     }
 
     // div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
-                                  SI5351_CLK_DRIVE_STRENGTH_2MA);
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6, drive_strength);
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
                                   SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
@@ -378,8 +376,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
 
   case 2:
     // div by 4 mode. both PLL A and B are dedicated for CLK0, CLK1
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4,
-                                  SI5351_CLK_DRIVE_STRENGTH_2MA);
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4, drive_strength);
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
                                   SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);