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https://github.com/juribeparada/MMDVM_HS.git
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Update the ADF7021 parameters for M17.
This commit is contained in:
Jonathan Naylor
parent
3f83f671a3
commit
dc2171bef7
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@ -424,7 +424,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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// Dev: +1 symb 2700/900 Hz, symb rate = 4800
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ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
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ADF7021_REG10 = ADF7021_REG10_YSF;
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@ -685,7 +685,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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// Dev: +1 symb 2700/900 Hz, symb rate = 4800
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ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
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ADF7021_REG10 = ADF7021_REG10_YSF;
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29
ADF7021.h
29
ADF7021.h
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@ -1,4 +1,5 @@
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/*
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* Copyright (C) 2020 by Jonathan Naylor G4KLX
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* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
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* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
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* Copyright (C) 2017 by Danilo DB4PLE
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@ -52,7 +53,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Support for ADF7021-N version:
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// #define ADF7021_N_VER
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// Enable AFC support for DMR, YSF and P25 (experimental):
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// Enable AFC support for DMR, YSF, P25, and M17 (experimental):
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// (AFC is already enabled by default in D-Star)
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// #define ADF7021_ENABLE_4FSK_AFC
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@ -65,7 +66,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// R = 4
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// DEMOD_CLK = 2.4576 MHz (DSTAR)
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// DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25)
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// DEMOD_CLK = 7.3728 MHz (YSF_H)
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// DEMOD_CLK = 7.3728 MHz (YSF_H, M17)
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// DEMOD CLK = 3.6864 MHz (NXDN)
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// DEMOD_CLK = 7.3728 MHz (POCSAG)
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#define ADF7021_PFD 3686400.0
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@ -87,7 +88,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DEV_P25 22U
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#endif
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#define ADF7021_DEV_NXDN 13U
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#define ADF7021_DEV_M17 28U // XXX FIXME
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#define ADF7021_DEV_M17 28U
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#define ADF7021_DEV_POCSAG 160U
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// TX/RX CLOCK register (REG 03)
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@ -98,7 +99,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG3_YSF_H 0x2A4C0493
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#define ADF7021_REG3_P25 0x2A4C04D3
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#define ADF7021_REG3_NXDN 0x2A4C04D3
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#define ADF7021_REG3_M17 0x2A4C04D3 // XXX FIXME
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#define ADF7021_REG3_M17 0x2A4C04D3
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#else
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#define ADF7021_REG3_DMR 0x2A4C80D3
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#define ADF7021_REG3_YSF_L 0x2A4C80D3
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@ -117,7 +118,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DISC_BW_YSF_H 516U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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#define ADF7021_DISC_BW_NXDN 295U // K=32
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#define ADF7021_DISC_BW_M17 459U // XXX FIXME
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#define ADF7021_DISC_BW_M17 393U // K=32 XXX FIXME
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#define ADF7021_DISC_BW_POCSAG 406U // K=22
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// Post demodulator bandwith (REG 04)
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@ -144,7 +145,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_YSF 0x01FE473A
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#define ADF7021_REG10_P25 0x01FE473A
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#define ADF7021_REG10_NXDN 0x01FE473A
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#define ADF7021_REG10_M17 0x01FE473A // XXX FIXME
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#define ADF7021_REG10_M17 0x01FE473A
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#if defined(ADF7021_AFC_POS)
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#define AFC_OFFSET_DMR -250
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#define AFC_OFFSET_YSF -250
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@ -163,7 +164,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_YSF 0x049E472A
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#define ADF7021_REG10_P25 0x049E472A
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#define ADF7021_REG10_NXDN 0x049E472A
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#define ADF7021_REG10_M17 0x049E472A // XXX FIXME
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#define ADF7021_REG10_M17 0x049E472A
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#define AFC_OFFSET_DMR 0
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#define AFC_OFFSET_YSF 0
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#define AFC_OFFSET_P25 0
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@ -176,7 +177,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// R = 2
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// DEMOD_CLK = 2.4576 MHz (DSTAR)
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// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25)
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// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25, M17)
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// DEMOD_CLK = 3.0720 MHz (NXDN)
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// DEMOD_CLK = 6.1440 MHz (POCSAG)
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#define ADF7021_PFD 6144000.0
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@ -198,7 +199,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DEV_P25 13U
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#endif
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#define ADF7021_DEV_NXDN 8U
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#define ADF7021_DEV_M17 17U // XXX FIXME
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#define ADF7021_DEV_M17 17U
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#define ADF7021_DEV_POCSAG 96U
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// TX/RX CLOCK register (REG 03)
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@ -209,14 +210,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG3_YSF_H 0x29EC0493
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#define ADF7021_REG3_P25 0x29EC0493
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#define ADF7021_REG3_NXDN 0x29EC0493
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#define ADF7021_REG3_M17 0x29EC0493 // XXX FIXME
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#define ADF7021_REG3_M17 0x29EC0493
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#else
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#define ADF7021_REG3_DMR 0x29ECA093
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#define ADF7021_REG3_YSF_L 0x29ECA093
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#define ADF7021_REG3_YSF_H 0x29ECA093
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#define ADF7021_REG3_P25 0x29ECA093
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#define ADF7021_REG3_NXDN 0x29ECA113
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#define ADF7021_REG3_M17 0x29ECA093 // XXX FIXME
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#define ADF7021_REG3_M17 0x29ECA093
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#endif
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#define ADF7021_REG3_POCSAG 0x29EE8093
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@ -228,7 +229,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DISC_BW_YSF_H 430U // K=28
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#define ADF7021_DISC_BW_P25 493U // K=32
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#define ADF7021_DISC_BW_NXDN 246U // K=32
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#define ADF7021_DISC_BW_M17 393U // XXX FIXME
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#define ADF7021_DISC_BW_M17 491U // K=32 XXX FIXME
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#define ADF7021_DISC_BW_POCSAG 338U // K=22
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// Post demodulator bandwith (REG 04)
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@ -255,7 +256,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_YSF 0x01FE557A
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#define ADF7021_REG10_P25 0x01FE557A
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#define ADF7021_REG10_NXDN 0x01FE557A
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#define ADF7021_REG10_M17 0x01FE557A // XXX FIXME
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#define ADF7021_REG10_M17 0x01FE557A
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#if defined(ADF7021_AFC_POS)
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#define AFC_OFFSET_DMR -250
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#define AFC_OFFSET_YSF -250
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@ -274,7 +275,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_YSF 0x049E556A
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#define ADF7021_REG10_P25 0x049E556A
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#define ADF7021_REG10_NXDN 0x049E556A
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#define ADF7021_REG10_M17 0x049E556A // XXX FIXME
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#define ADF7021_REG10_M17 0x049E556A
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#define AFC_OFFSET_DMR 0
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#define AFC_OFFSET_YSF 0
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#define AFC_OFFSET_P25 0
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