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https://github.com/juribeparada/MMDVM_HS.git
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Adding 19.68 MHz TCXO support
This commit is contained in:
Andy CA6JAU
parent
7d6d179846
commit
d71b7aa053
4 changed files with 186 additions and 67 deletions
135
ADF7021.cpp
135
ADF7021.cpp
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@ -22,7 +22,7 @@
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#include "Config.h"
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#if defined(ADF7021)
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#if defined(ENABLE_ADF7021)
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#include "Globals.h"
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#include "IO.h"
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@ -67,8 +67,8 @@ void Send_REG0_RX()
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ADF7021_RX_REG0 = (uint32_t)0b0000;
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ADF7021_RX_REG0 |= (uint32_t)0b01011 << 27; // mux regulator/uart enabled/receive
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ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; //frequency;
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ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; //frequency;
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ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; // frequency;
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ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; // frequency;
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AD7021_control_byte = ADF7021_RX_REG0;
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Send_AD7021_control();
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@ -87,10 +87,10 @@ void Send_REG0_TX()
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divider = (divider - N_divider) * 32768;
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F_divider = floor(divider + 0.5);
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ADF7021_TX_REG0 = (uint32_t)0b0000; // register 0
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ADF7021_TX_REG0 |= (uint32_t)0b01010 << 27; // mux regulator/uart enabled/transmit
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ADF7021_TX_REG0 |= (uint32_t)N_divider << 19; //frequency;
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ADF7021_TX_REG0 |= (uint32_t)F_divider << 4; //frequency;
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ADF7021_TX_REG0 = (uint32_t) 0b0000; // register 0
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ADF7021_TX_REG0 |= (uint32_t) 0b01010 << 27; // mux regulator/uart enabled/transmit
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ADF7021_TX_REG0 |= (uint32_t) N_divider << 19; // frequency;
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ADF7021_TX_REG0 |= (uint32_t) F_divider << 4; // frequency;
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AD7021_control_byte = ADF7021_TX_REG0;
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Send_AD7021_control();
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@ -98,88 +98,101 @@ void Send_REG0_TX()
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void CIO::ifConf()
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{
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG13 = 0;
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if (m_dstarEnable) {
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// Dev: 1200 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C4193;
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ADF7021_REG4 = 0x00A82A94;
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ADF7021_REG13 = 0x0000000D;
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ADF7021_REG3 = ADF7021_REG3_DSTAR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
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ADF7021_REG4 |= (uint32_t) 0b1 << 7;
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ADF7021_REG4 |= (uint32_t) 0b10 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b00 << 30; // IF filter
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ADF7021_REG2 = (uint32_t)0b00 << 28; // clock normal
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ADF7021_REG2 |= (uint32_t)0b000101010 << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b001 << 4; // modulation (GMSK)
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DSTAR << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
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}
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else if (m_dmrEnable) {
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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ADF7021_REG3 = ADF7021_REG3_DMR;
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// K=32
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = 0x0000033D;
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)24U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DMR << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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else if (m_ysfEnable) {
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// Dev: +1 symb 900 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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ADF7021_REG3 = ADF7021_REG3_YSF;
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// K=28
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)344U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_YSF << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = 0x000003BD;
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)32U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_YSF << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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else if (m_p25Enable) {
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// Dev: +1 symb 600 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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ADF7021_REG3 = ADF7021_REG3_P25;
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// K=32
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = 0x000002DD;
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)22U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_P25 << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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// VCO/OSCILLATOR (REG1)
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if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) )
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AD7021_control_byte = 0x021F5041; // VHF, external VCO
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AD7021_control_byte = ADF7021_REG1_VHF; // VHF, external VCO
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else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
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AD7021_control_byte = 0x00575041; // UHF, internal VCO
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AD7021_control_byte = ADF7021_REG1_UHF; // UHF, internal VCO
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Send_AD7021_control();
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@ -192,13 +205,13 @@ void CIO::ifConf()
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Send_AD7021_control();
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// IF FILTER (5)
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AD7021_control_byte = 0x000024F5;
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AD7021_control_byte = ADF7021_REG5;
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Send_AD7021_control();
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// MODULATION (2)
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ADF7021_REG2 |= (uint32_t)0b0010; // register 2
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ADF7021_REG2 |= (uint32_t)m_power << 13; // power level
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ADF7021_REG2 |= (uint32_t)0b110001 << 7; // PA
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ADF7021_REG2 |= (uint32_t) 0b0010; // register 2
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ADF7021_REG2 |= (uint32_t) m_power << 13; // power level
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ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
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AD7021_control_byte = ADF7021_REG2;
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Send_AD7021_control();
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@ -207,15 +220,15 @@ void CIO::ifConf()
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Send_AD7021_control();
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// IF FINE CAL (fine cal, defaults) (6)
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AD7021_control_byte = 0x05080B16;
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AD7021_control_byte = ADF7021_REG6;
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Send_AD7021_control();
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// AGC (auto, defaults) (9)
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AD7021_control_byte = 0x000231E9; // auto
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AD7021_control_byte = 0x000231E9;
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Send_AD7021_control();
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// AFC (off, defaults) (10)
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AD7021_control_byte = 0x3296472A; // off
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AD7021_control_byte = ADF7021_REG10;
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Send_AD7021_control();
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// SYNC WORD DET (11)
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