Merge pull request #80 from phl0/POCSAGcal4thTry

Add POCSAG cal basics
This commit is contained in:
Andy CA6JAU 2019-01-31 16:39:25 -03:00 committed by GitHub
commit b7a6edef6d
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5 changed files with 59 additions and 8 deletions

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@ -1,6 +1,7 @@
/*
* Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
* Copyright (C) 2019 by Florian Wolters DF2ET
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -48,7 +49,8 @@ enum MMDVM_STATE {
STATE_CWID = 97,
STATE_DMRCAL = 98,
STATE_DSTARCAL = 99,
STATE_INTCAL = 100
STATE_INTCAL = 100,
STATE_POCSAGCAL = 101
};
const uint8_t MARK_SLOT1 = 0x08U;

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@ -3,6 +3,7 @@
* Copyright (C) 2016 by Mathis Schmieder DB9MAT
* Copyright (C) 2016 by Colin Durbridge G4EML
* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
* Copyright (C) 2019 by Florian Wolters DF2ET
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -120,8 +121,11 @@ void loop()
if (m_nxdnEnable && m_modemState == STATE_NXDN)
nxdnTX.process();
if (m_pocsagEnable && (m_modemState == STATE_POCSAG || pocsagTX.busy()))
if (m_pocsagEnable && (m_modemState == STATE_POCSAG || pocsagTX.busy())) {
if (m_calState == STATE_POCSAGCAL)
pocsagTX.setCal(true);
pocsagTX.process();
}
if (m_calState == STATE_DMRCAL || m_calState == STATE_DMRDMO1K || m_calState == STATE_INTCAL)
calDMR.process();

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@ -1,6 +1,7 @@
/*
* Copyright (C) 2015,2016,2017,2018 by Jonathan Naylor G4KLX
* Copyright (C) 2018 by Andy Uribe CA6JAU
* Copyright (C) 2019 by Florian Wolters DF2ET
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -28,12 +29,18 @@ m_poBuffer(),
m_poLen(0U),
m_poPtr(0U),
m_txDelay(POCSAG_PREAMBLE_LENGTH_BYTES),
m_delay(false)
m_delay(false),
m_cal(false)
{
}
void CPOCSAGTX::process()
{
if (m_cal) {
m_delay = false;
createCal();
}
if (m_poLen == 0U && m_buffer.getData() > 0U) {
if (!m_tx) {
m_delay = true;
@ -80,8 +87,8 @@ bool CPOCSAGTX::busy()
uint8_t CPOCSAGTX::writeData(const uint8_t* data, uint8_t length)
{
if (length != POCSAG_FRAME_LENGTH_BYTES)
return 4U;
//if (length != POCSAG_FRAME_LENGTH_BYTES)
//return 4U;
uint16_t space = m_buffer.getSpace();
if (space < POCSAG_FRAME_LENGTH_BYTES)
@ -120,3 +127,20 @@ uint8_t CPOCSAGTX::getSpace() const
{
return m_buffer.getSpace() / POCSAG_FRAME_LENGTH_BYTES;
}
void CPOCSAGTX::setCal(bool start)
{
m_cal = start ? true : false;
}
void CPOCSAGTX::createCal()
{
// 600 Hz square wave generation
for (unsigned int i = 0U; i < POCSAG_FRAME_LENGTH_BYTES; i++) {
m_poBuffer[i] = 0xAAU;
}
m_poLen = POCSAG_FRAME_LENGTH_BYTES;
m_poPtr = 0U;
}

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@ -1,6 +1,7 @@
/*
* Copyright (C) 2015,2016,2017,2018 by Jonathan Naylor G4KLX
* Copyright (C) 2018 by Andy Uribe CA6JAU
* Copyright (C) 2019 by Florian Wolters DF2ET
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -28,6 +29,10 @@ public:
void setTXDelay(uint8_t delay);
void setCal(bool);
void createCal();
uint8_t getSpace() const;
void process();
@ -41,6 +46,7 @@ private:
uint16_t m_poPtr;
uint16_t m_txDelay;
bool m_delay;
bool m_cal;
void writeByte(uint8_t c);
};

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@ -2,6 +2,7 @@
* Copyright (C) 2013,2015,2016,2018 by Jonathan Naylor G4KLX
* Copyright (C) 2016 by Colin Durbridge G4EML
* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
* Copyright (C) 2019 by Florian Wolters DF2ET
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -234,7 +235,7 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
MMDVM_STATE modemState = MMDVM_STATE(data[3U]);
if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25 && modemState != STATE_NXDN && modemState != STATE_POCSAG && modemState != STATE_DSTARCAL && modemState != STATE_DMRCAL && modemState != STATE_DMRDMO1K && modemState != STATE_INTCAL && modemState != STATE_RSSICAL)
if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25 && modemState != STATE_NXDN && modemState != STATE_POCSAG && modemState != STATE_DSTARCAL && modemState != STATE_DMRCAL && modemState != STATE_DMRDMO1K && modemState != STATE_INTCAL && modemState != STATE_RSSICAL && modemState != STATE_POCSAGCAL)
return 4U;
if (modemState == STATE_DSTAR && !dstarEnable)
return 4U;
@ -289,6 +290,12 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
io.updateCal();
if (modemState == STATE_RSSICAL)
io.ifConf(STATE_DMR, true);
} else if (modemState == STATE_POCSAGCAL) {
m_pocsagEnable = true;
m_modemState = STATE_POCSAG;
m_calState = modemState;
if (m_firstCal)
io.updateCal();
}
else {
m_modemState = modemState;
@ -342,7 +349,7 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
io.printConf();
#endif
if (modemState == STATE_DMRCAL || modemState == STATE_DMRDMO1K || modemState == STATE_RSSICAL || modemState == STATE_INTCAL)
if (modemState == STATE_DMRCAL || modemState == STATE_DMRDMO1K || modemState == STATE_RSSICAL || modemState == STATE_INTCAL || modemState == STATE_POCSAGCAL)
m_firstCal = true;
return 0U;
@ -359,7 +366,7 @@ uint8_t CSerialPort::setMode(const uint8_t* data, uint8_t length)
if (modemState == m_modemState)
return 0U;
if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25 && modemState != STATE_NXDN && modemState != STATE_POCSAG && modemState != STATE_DSTARCAL && modemState != STATE_DMRCAL && modemState != STATE_DMRDMO1K && modemState != STATE_RSSICAL && modemState != STATE_INTCAL)
if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25 && modemState != STATE_NXDN && modemState != STATE_POCSAG && modemState != STATE_DSTARCAL && modemState != STATE_DMRCAL && modemState != STATE_DMRDMO1K && modemState != STATE_RSSICAL && modemState != STATE_INTCAL && modemState != STATE_POCSAGCAL)
return 4U;
if (modemState == STATE_DSTAR && !m_dstarEnable)
return 4U;
@ -380,6 +387,12 @@ uint8_t CSerialPort::setMode(const uint8_t* data, uint8_t length)
m_calState = modemState;
if (m_firstCal)
io.updateCal();
} else if (modemState == STATE_POCSAGCAL) {
m_pocsagEnable = true;
tmpState = STATE_POCSAG;
m_calState = modemState;
if (m_firstCal)
io.updateCal();
}
else {
tmpState = modemState;
@ -592,6 +605,8 @@ void CSerialPort::process()
case MMDVM_CAL_DATA:
if (m_calState == STATE_DMRCAL || m_calState == STATE_DMRDMO1K) {
err = calDMR.write(m_buffer + 3U, m_len - 3U);
} else if (m_calState == STATE_POCSAGCAL) {
err = pocsagTX.writeData(m_buffer + 3U, m_len - 3U);
} else if (m_calState == STATE_RSSICAL || m_calState == STATE_INTCAL) {
err = 0U;
}