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https://github.com/juribeparada/MMDVM_HS.git
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Add dummy register values for ADF7021
This commit is contained in:
Andy CA6JAU
parent
f1fe279408
commit
ae4431c884
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@ -865,6 +865,11 @@ uint16_t CIO::devP25()
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return (uint16_t)((ADF7021_PFD * ADF7021_DEV_P25) / (f_div * 65536));
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}
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uint16_t CIO::devNXDN()
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{
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return (uint16_t)((ADF7021_PFD * ADF7021_DEV_NXDN) / (f_div * 65536));
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}
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void CIO::printConf()
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{
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DEBUG1("MMDVM_HS FW configuration:");
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@ -876,6 +881,7 @@ void CIO::printConf()
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DEBUG2("YSF_H +1 sym dev (Hz):", devYSF_H());
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DEBUG2("YSF_L +1 sym dev (Hz):", devYSF_L());
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DEBUG2("P25 +1 sym dev (Hz):", devP25());
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DEBUG2("NXDN +1 sym dev (Hz):", devNXDN());
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}
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#endif
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24
ADF7021.h
24
ADF7021.h
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
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* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
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* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
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* Copyright (C) 2017 by Danilo DB4PLE
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*
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* Some of the code is based on work of Guus Van Dooren PE1PLM:
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@ -84,6 +84,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#else
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#define ADF7021_DEV_P25 22U
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#endif
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#define ADF7021_DEV_NXDN 22U
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x2A4C4193
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@ -92,11 +93,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG3_YSF_L 0x2A4C04D3
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#define ADF7021_REG3_YSF_H 0x2A4C0493
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#define ADF7021_REG3_P25 0x2A4C04D3
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#define ADF7021_REG3_NXDN 0x2A4C04D3
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#else
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#define ADF7021_REG3_DMR 0x2A4C80D3
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#define ADF7021_REG3_YSF_L 0x2A4C80D3
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#define ADF7021_REG3_YSF_H 0x2A4CC093
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#define ADF7021_REG3_P25 0x2A4C80D3
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#define ADF7021_REG3_NXDN 0x2A4C80D3
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#endif
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// Discriminator bandwith, demodulator (REG 04)
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@ -106,12 +109,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DISC_BW_YSF_L 393U // K=32
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#define ADF7021_DISC_BW_YSF_H 516U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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#define ADF7021_DISC_BW_NXDN 394U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 150U
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#define ADF7021_POST_BW_YSF 20U
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#define ADF7021_POST_BW_P25 6U
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#define ADF7021_POST_BW_NXDN 6U
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// IF filter (REG 05)
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#define ADF7021_REG5 0x000024F5
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@ -126,22 +131,27 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_DMR 0x01FE473A
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#define ADF7021_REG10_YSF 0x01FE473A
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#define ADF7021_REG10_P25 0x01FE473A
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#define ADF7021_REG10_NXDN 0x01FE473A
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#if defined(ADF7021_AFC_POS)
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#define AFC_OFFSET_DMR -250
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#define AFC_OFFSET_YSF -250
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#define AFC_OFFSET_P25 -250
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#define AFC_OFFSET_NXDN -250
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#else
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#define AFC_OFFSET_DMR 250
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#define AFC_OFFSET_YSF 250
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#define AFC_OFFSET_P25 250
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#define AFC_OFFSET_NXDN 250
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#endif
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#else
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#define ADF7021_REG10_DMR 0x049E472A
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#define ADF7021_REG10_YSF 0x049E472A
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#define ADF7021_REG10_P25 0x049E472A
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#define ADF7021_REG10_NXDN 0x049E472A
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#define AFC_OFFSET_DMR 0
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#define AFC_OFFSET_YSF 0
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#define AFC_OFFSET_P25 0
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#define AFC_OFFSET_NXDN 0
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#endif
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/****** Support for 12.2880 MHz TCXO ******/
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@ -168,6 +178,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#else
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#define ADF7021_DEV_P25 13U
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#endif
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#define ADF7021_DEV_NXDN 13U
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x29EC4153
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@ -176,11 +187,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG3_YSF_L 0x29EC0493
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#define ADF7021_REG3_YSF_H 0x29EC0493
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#define ADF7021_REG3_P25 0x29EC0493
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#define ADF7021_REG3_NXDN 0x29EC0493
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#else
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#define ADF7021_REG3_DMR 0x29ECA093
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#define ADF7021_REG3_YSF_L 0x29ECA093
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#define ADF7021_REG3_YSF_H 0x29ECA093
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#define ADF7021_REG3_P25 0x29ECA093
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#define ADF7021_REG3_NXDN 0x29ECA093
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#endif
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// Discriminator bandwith, demodulator (REG 04)
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@ -190,12 +203,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DISC_BW_YSF_L 491U // K=32
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#define ADF7021_DISC_BW_YSF_H 430U // K=28
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#define ADF7021_DISC_BW_P25 493U // K=32
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#define ADF7021_DISC_BW_NXDN 493U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 150U
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#define ADF7021_POST_BW_YSF 20U
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#define ADF7021_POST_BW_P25 6U
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#define ADF7021_POST_BW_NXDN 6U
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// IF filter (REG 05)
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#define ADF7021_REG5 0x00001ED5
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@ -210,22 +225,27 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_REG10_DMR 0x01FE557A
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#define ADF7021_REG10_YSF 0x01FE557A
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#define ADF7021_REG10_P25 0x01FE557A
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#define ADF7021_REG10_NXDN 0x01FE557A
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#if defined(ADF7021_AFC_POS)
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#define AFC_OFFSET_DMR -250
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#define AFC_OFFSET_YSF -250
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#define AFC_OFFSET_P25 -250
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#define AFC_OFFSET_NXDN -250
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#else
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#define AFC_OFFSET_DMR 250
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#define AFC_OFFSET_YSF 250
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#define AFC_OFFSET_P25 250
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#define AFC_OFFSET_NXDN 250
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#endif
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#else
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#define ADF7021_REG10_DMR 0x049E556A
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#define ADF7021_REG10_YSF 0x049E556A
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#define ADF7021_REG10_P25 0x049E556A
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#define ADF7021_REG10_NXDN 0x049E556A
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#define AFC_OFFSET_DMR 0
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#define AFC_OFFSET_YSF 0
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#define AFC_OFFSET_P25 0
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#define AFC_OFFSET_NXDN 0
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#endif
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#endif
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@ -238,6 +258,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_SLICER_TH_YSF_L 35U
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#define ADF7021_SLICER_TH_YSF_H 69U
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#define ADF7021_SLICER_TH_P25 43U
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#define ADF7021_SLICER_TH_NXDN 43U
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#else
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@ -246,6 +267,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_SLICER_TH_YSF_L 38U
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#define ADF7021_SLICER_TH_YSF_H 75U
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#define ADF7021_SLICER_TH_P25 47U
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#define ADF7021_SLICER_TH_NXDN 47U
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#endif
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5
IO.h
5
IO.h
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
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* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
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* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
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* Copyright (C) 2017 by Danilo DB4PLE
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* This program is free software; you can redistribute it and/or modify
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@ -127,6 +127,7 @@ public:
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uint16_t devYSF_H(void);
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uint16_t devYSF_L(void);
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uint16_t devP25(void);
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uint16_t devNXDN(void);
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void printConf();
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private:
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@ -144,7 +145,7 @@ private:
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uint32_t m_scanPauseCnt;
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uint8_t m_scanPos;
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uint8_t m_TotalModes;
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MMDVM_STATE m_Modes[4];
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MMDVM_STATE m_Modes[5];
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bool m_ledValue;
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volatile uint32_t m_watchdog;
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2015 by Jonathan Naylor G4KLX
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* Copyright (C) 2017 by Andy Uribe CA6JAU
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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