mirror of
https://github.com/juribeparada/MMDVM_HS.git
synced 2025-12-06 07:12:08 +01:00
Some contextual cleanups.
This commit is contained in:
Jonathan Naylor
parent
023462a86d
commit
92597e0d00
97
ADF7021.cpp
97
ADF7021.cpp
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@ -54,10 +54,8 @@ uint16_t m_pocsagDev;
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static void Send_AD7021_control_shift()
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{
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int AD7021_counter;
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for(AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
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if(bitRead(AD7021_control_word, AD7021_counter) == HIGH)
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for (int AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
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if (bitRead(AD7021_control_word, AD7021_counter) == HIGH)
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io.SDATA_pin(HIGH);
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else
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io.SDATA_pin(LOW);
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@ -67,6 +65,7 @@ static void Send_AD7021_control_shift()
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io.dlybit();
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io.SCLK_pin(LOW);
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}
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// to keep SDATA signal at defined level when idle (not required)
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io.SDATA_pin(LOW);
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}
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@ -82,9 +81,8 @@ void Send_AD7021_control(bool doSle)
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{
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Send_AD7021_control_shift();
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if (doSle) {
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if (doSle)
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Send_AD7021_control_slePulse();
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}
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}
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#if defined(DUPLEX)
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@ -99,9 +97,8 @@ void Send_AD7021_control2(bool doSle)
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{
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Send_AD7021_control_shift();
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if (doSle) {
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if (doSle)
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Send_AD7021_control_sle2Pulse();
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}
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}
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#endif
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@ -110,15 +107,14 @@ uint16_t CIO::readRSSI()
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{
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uint32_t AD7021_RB;
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uint16_t RB_word = 0U;
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int AD7021_counter;
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uint8_t RB_code, gain_code, gain_corr;
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// Register 7, readback enable, ADC RSSI mode
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AD7021_RB = 0x0147;
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// Send control register
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for(AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
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if(bitRead(AD7021_RB, AD7021_counter) == HIGH)
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for (int AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
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if (bitRead(AD7021_RB, AD7021_counter) == HIGH)
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SDATA_pin(HIGH);
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else
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SDATA_pin(LOW);
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@ -143,16 +139,15 @@ uint16_t CIO::readRSSI()
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dlybit();
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// Read SREAD pin
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for(AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
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for (int AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
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SCLK_pin(HIGH);
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dlybit();
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if( (AD7021_counter != 17) && (AD7021_counter != 0) )
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RB_word |= ( (SREAD_pin() & 0x01) << (AD7021_counter-1) );
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if ((AD7021_counter != 17) && (AD7021_counter != 0))
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RB_word |= ((SREAD_pin() & 0x01) << (AD7021_counter - 1));
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SCLK_pin(LOW);
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dlybit();
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}
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#if defined(DUPLEX)
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@ -223,7 +218,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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#endif
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// Toggle CE pin for ADF7021 reset
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if(reset) {
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if (reset) {
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CE_pin(LOW);
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delay_reset();
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CE_pin(HIGH);
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@ -231,28 +226,24 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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}
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// Check frequency band
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if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
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if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
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} else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
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} else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
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} else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
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div2 = 2U;
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}
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else {
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} else {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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if(div2 == 1U)
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if (div2 == 1U)
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f_div = 2U;
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else
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f_div = 1U;
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@ -282,10 +273,10 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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break;
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}
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if( div2 == 1U )
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if (div2 == 1U)
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divider = (m_frequency_rx - 100000 + AFC_OFFSET) / (ADF7021_PFD / 2U);
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else
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divider = (m_frequency_rx - 100000 + (2*AFC_OFFSET)) / ADF7021_PFD;
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divider = (m_frequency_rx - 100000 + (2 * AFC_OFFSET)) / ADF7021_PFD;
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m_RX_N_divider = floor(divider);
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divider = (divider - m_RX_N_divider) * 32768;
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@ -302,7 +293,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_RX_REG0 |= (uint32_t) m_RX_N_divider << 19; // frequency;
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ADF7021_RX_REG0 |= (uint32_t) m_RX_F_divider << 4; // frequency;
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if( div2 == 1U )
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if (div2 == 1U)
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divider = m_frequency_tx / (ADF7021_PFD / 2U);
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else
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divider = m_frequency_tx / ADF7021_PFD;
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@ -424,7 +415,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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// Dev: +1 symb 900/450 Hz, symb rate = 4800
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ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
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ADF7021_REG10 = ADF7021_REG10_YSF;
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@ -623,7 +614,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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}
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#if defined(DUPLEX)
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if(m_duplex && (modemState != STATE_CWID && modemState != STATE_POCSAG))
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if (m_duplex && (modemState != STATE_CWID && modemState != STATE_POCSAG))
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ifConf2(modemState);
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#endif
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}
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@ -685,7 +676,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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break;
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case STATE_YSF:
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// Dev: +1 symb 2700/900 Hz, symb rate = 4800
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// Dev: +1 symb 900/450 Hz, symb rate = 4800
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ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
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ADF7021_REG10 = ADF7021_REG10_YSF;
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@ -862,25 +853,23 @@ void CIO::interrupt()
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// possibly this is a design problem of the RF7021 board or too long wires
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// on the breadboard build
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// but normally this will not hurt too much
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if (clk == last_clk) {
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if (clk == last_clk)
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return;
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} else {
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else
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last_clk = clk;
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}
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// we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
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if (m_tx && clk == 0U) {
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m_txBuffer.get(bit, m_control);
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even = !even;
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#if defined(BIDIR_DATA_PIN)
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if(bit)
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if (bit)
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RXD_pin_write(HIGH);
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else
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RXD_pin_write(LOW);
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#else
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if(bit)
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if (bit)
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TXD_pin(HIGH);
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else
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TXD_pin(LOW);
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@ -912,7 +901,7 @@ void CIO::interrupt()
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// we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
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if (!m_tx && clk == 1U && !m_duplex) {
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if(RXD_pin())
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if (RXD_pin())
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bit = 1U;
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else
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bit = 0U;
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@ -920,7 +909,7 @@ void CIO::interrupt()
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m_rxBuffer.put(bit, m_control);
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}
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if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
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if (torx_request && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
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// that is absolutely crucial in 4FSK, see datasheet:
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// enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
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delay_us(26U);
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@ -946,10 +935,10 @@ void CIO::interrupt()
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m_modeTimerCnt++;
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m_int1counter++;
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if(m_scanPauseCnt >= SCAN_PAUSE)
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if (m_scanPauseCnt >= SCAN_PAUSE)
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m_scanPauseCnt = 0U;
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if(m_scanPauseCnt != 0U)
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if (m_scanPauseCnt != 0U)
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m_scanPauseCnt++;
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}
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@ -958,8 +947,8 @@ void CIO::interrupt2()
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{
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uint8_t bit = 0U;
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if(m_duplex) {
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if(RXD2_pin())
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if (m_duplex) {
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if (RXD2_pin())
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bit = 1U;
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else
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bit = 0U;
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@ -1003,7 +992,7 @@ void CIO::setRX(bool doSle)
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Data_dir_out(false); // Data pin input mode
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#endif
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if(!doSle) {
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if (!doSle) {
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torx_request = true;
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while(torx_request) { asm volatile ("nop"); }
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}
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@ -1036,28 +1025,24 @@ void CIO::updateCal()
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float divider;
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// Check frequency band
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if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
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if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
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} else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
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} else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
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} else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
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ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
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div2 = 2U;
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}
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else {
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} else {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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if(div2 == 1U)
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if (div2 == 1U)
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f_div = 2U;
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else
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f_div = 1U;
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@ -1083,7 +1068,7 @@ void CIO::updateCal()
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AD7021_control_word = ADF7021_REG2;
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Send_AD7021_control();
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if( div2 == 1U )
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if (div2 == 1U)
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divider = m_frequency_tx / (ADF7021_PFD / 2U);
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else
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divider = m_frequency_tx / ADF7021_PFD;
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