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Andy CA6JAU
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254
ADF7021.cpp
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254
ADF7021.cpp
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/*
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* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
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* Copyright (C) 2016, 2017 by Andy Uribe CA6JAU
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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#if defined(ADF7021)
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#include "Globals.h"
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#include "IO.h"
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#include "ADF7021.h"
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#include <math.h>
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volatile uint32_t AD7021_control_byte;
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volatile int AD7021_counter;
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void dlybit(void)
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{
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volatile unsigned int delay;
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for(delay = 0;delay<5;delay++);
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}
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void Send_AD7021_control()
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{
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for(AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
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if(bitRead(AD7021_control_byte, AD7021_counter) == HIGH)
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io.SDATA_pin(HIGH);
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else
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io.SDATA_pin(LOW);
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io.SCLK_pin(HIGH);
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dlybit();
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io.SCLK_pin(LOW);
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dlybit();
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}
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io.SLE_pin(HIGH);
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dlybit();
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io.SLE_pin(LOW);
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io.SDATA_pin(LOW);
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}
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void Send_REG0_RX()
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{
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uint32_t ADF7021_RX_REG0;
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float divider;
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uint8_t N_divider;
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uint16_t F_divider;
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divider = (m_frequency_rx - 100000) / (ADF7021_PFD / 2.0);
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N_divider = floor(divider);
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divider = (divider - N_divider) * 32768;
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F_divider = floor(divider + 0.5);
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ADF7021_RX_REG0 = (uint32_t)0b0000;
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ADF7021_RX_REG0 |= (uint32_t)0b01011 << 27; // mux regulator/uart enabled/receive
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ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; //frequency;
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ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; //frequency;
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AD7021_control_byte = ADF7021_RX_REG0;
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Send_AD7021_control();
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}
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void Send_REG0_TX()
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{
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uint32_t ADF7021_TX_REG0;
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float divider;
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uint8_t N_divider;
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uint16_t F_divider;
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divider = m_frequency_tx / (ADF7021_PFD / 2.0);
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N_divider = floor(divider);
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divider = (divider - N_divider) * 32768;
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F_divider = floor(divider + 0.5);
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ADF7021_TX_REG0 = (uint32_t)0b0000; // register 0
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ADF7021_TX_REG0 |= (uint32_t)0b01010 << 27; // mux regulator/uart enabled/transmit
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ADF7021_TX_REG0 |= (uint32_t)N_divider << 19; //frequency;
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ADF7021_TX_REG0 |= (uint32_t)F_divider << 4; //frequency;
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AD7021_control_byte = ADF7021_TX_REG0;
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Send_AD7021_control();
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}
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void CIO::ifConf()
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{
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG13 = 0;
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if (m_dstarEnable) {
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// Dev: 1200 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C4193;
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ADF7021_REG4 = 0x00A82A94;
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ADF7021_REG13 = 0x0000000D;
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ADF7021_REG2 = (uint32_t)0b00 << 28; // clock normal
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ADF7021_REG2 |= (uint32_t)0b000101010 << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b001 << 4; // modulation (GMSK)
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}
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else if (m_dmrEnable) {
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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// K=32
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG13 = 0x0000033D;
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)24U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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}
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else if (m_ysfEnable) {
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// Dev: +1 symb 900 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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// K=28
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)344U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG13 = 0x000003BD;
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)32U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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}
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else if (m_p25Enable) {
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// Dev: +1 symb 600 Hz, symb rate = 4800
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ADF7021_REG3 = 0x2A4C80D3;
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// K=32
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ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t)0b0 << 7;
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ADF7021_REG4 |= (uint32_t)0b11 << 8;
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ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
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ADF7021_REG13 = 0x000002DD;
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ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t)22U << 19; // deviation
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ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
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}
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// VCO/OSCILLATOR (REG1)
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if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) )
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AD7021_control_byte = 0x021F5041; // VHF, external VCO
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else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
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AD7021_control_byte = 0x00575041; // UHF, internal VCO
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Send_AD7021_control();
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// TX/RX CLOCK (3)
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AD7021_control_byte = ADF7021_REG3;
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Send_AD7021_control();
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// DEMOD (4)
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AD7021_control_byte = ADF7021_REG4;
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Send_AD7021_control();
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// IF FILTER (5)
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AD7021_control_byte = 0x000024F5;
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Send_AD7021_control();
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// MODULATION (2)
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ADF7021_REG2 |= (uint32_t)0b0010; // register 2
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ADF7021_REG2 |= (uint32_t)m_power << 13; // power level
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ADF7021_REG2 |= (uint32_t)0b110001 << 7; // PA
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AD7021_control_byte = ADF7021_REG2;
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Send_AD7021_control();
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// TEST MODE (disabled) (15)
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AD7021_control_byte = 0x000E000F;
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Send_AD7021_control();
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// IF FINE CAL (fine cal, defaults) (6)
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AD7021_control_byte = 0x05080B16;
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Send_AD7021_control();
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// AGC (auto, defaults) (9)
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AD7021_control_byte = 0x000231E9; // auto
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Send_AD7021_control();
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// AFC (off, defaults) (10)
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AD7021_control_byte = 0x3296472A; // off
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Send_AD7021_control();
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// SYNC WORD DET (11)
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AD7021_control_byte = 0x0000003B;
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Send_AD7021_control();
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// SWD/THRESHOLD (12)
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AD7021_control_byte = 0x0000010C;
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Send_AD7021_control();
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// 3FSK/4FSK DEMOD (13)
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AD7021_control_byte = ADF7021_REG13;
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Send_AD7021_control();
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}
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//======================================================================================================================
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void CIO::setTX()
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{
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PTT_pin(HIGH);
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LED_pin(LOW);
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Send_REG0_TX();
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}
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//======================================================================================================================
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void CIO::setRX()
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{
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PTT_pin(LOW);
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LED_pin(HIGH);
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delay_rx();
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Send_REG0_RX();
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}
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#endif
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