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https://github.com/jankae/LibreVNA.git
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196 lines
6.6 KiB
VHDL
196 lines
6.6 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:41:17 06/07/2022
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-- Design Name:
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-- Module Name: /home/jan/Projekte/LibreVNA/FPGA/Generator/test_modulator.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: Modulator
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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USE ieee.numeric_std.ALL;
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ENTITY test_modulator IS
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END test_modulator;
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ARCHITECTURE behavior OF test_modulator IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Modulator
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0);
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SAMPLE_DATA : IN std_logic_vector(7 downto 0);
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SAMPLE_LATCH : IN std_logic;
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OVERFLOW : OUT std_logic;
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UNDERFLOW : OUT std_logic;
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THRESHOLD_LEVEL : IN std_logic_vector(10 downto 0);
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THRESHOLD_CROSSED : OUT std_logic;
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FREQ_CENTER : IN std_logic_vector(32 downto 0);
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FREQ_DEVIATION : IN std_logic_vector(25 downto 0);
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MIN_ATTENUATION : IN std_logic_vector(6 downto 0);
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AMPLITUDE_DEPTH : IN std_logic_vector(6 downto 0);
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FREQUENCY : OUT std_logic_vector(32 downto 0);
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ATTENUATOR : OUT std_logic_vector(6 downto 0);
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NEW_OUTPUT : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal SAMPLE_FREQ_WORD : std_logic_vector(15 downto 0) := (others => '0');
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signal SAMPLE_DATA : std_logic_vector(7 downto 0) := (others => '0');
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signal SAMPLE_LATCH : std_logic := '0';
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signal THRESHOLD_LEVEL : std_logic_vector(10 downto 0) := (others => '0');
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signal FREQ_CENTER : std_logic_vector(32 downto 0) := (others => '0');
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signal FREQ_DEVIATION : std_logic_vector(25 downto 0) := (others => '0');
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signal MIN_ATTENUATION : std_logic_vector(6 downto 0) := (others => '0');
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signal AMPLITUDE_DEPTH : std_logic_vector(6 downto 0) := (others => '0');
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--Outputs
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signal OVERFLOW : std_logic;
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signal UNDERFLOW : std_logic;
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signal THRESHOLD_CROSSED : std_logic;
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signal FREQUENCY : std_logic_vector(32 downto 0);
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signal ATTENUATOR : std_logic_vector(6 downto 0);
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signal NEW_OUTPUT : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Modulator PORT MAP (
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CLK => CLK,
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RESET => RESET,
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SAMPLE_FREQ_WORD => SAMPLE_FREQ_WORD,
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SAMPLE_DATA => SAMPLE_DATA,
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SAMPLE_LATCH => SAMPLE_LATCH,
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OVERFLOW => OVERFLOW,
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UNDERFLOW => UNDERFLOW,
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THRESHOLD_LEVEL => THRESHOLD_LEVEL,
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THRESHOLD_CROSSED => THRESHOLD_CROSSED,
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FREQ_CENTER => FREQ_CENTER,
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FREQ_DEVIATION => FREQ_DEVIATION,
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MIN_ATTENUATION => MIN_ATTENUATION,
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AMPLITUDE_DEPTH => AMPLITUDE_DEPTH,
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FREQUENCY => FREQUENCY,
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ATTENUATOR => ATTENUATOR,
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NEW_OUTPUT => NEW_OUTPUT
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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RESET <= '1';
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-- hold reset state for 100 ns.
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wait for 100 ns;
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SAMPLE_FREQ_WORD <= std_logic_vector(to_unsigned(32768, 16));
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THRESHOLD_LEVEL <= std_logic_vector(to_unsigned(5, 11));
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FREQ_CENTER <= std_logic_vector(to_unsigned(134217728, 33));
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FREQ_DEVIATION <= std_logic_vector(to_unsigned(16777216, 26));
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MIN_ATTENUATION <= std_logic_vector(to_unsigned(64, 7));
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AMPLITUDE_DEPTH <= std_logic_vector(to_unsigned(127, 7));
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wait for CLK_period*10;
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-- release reset
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RESET <= '0';
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-- add samples
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(0, 8));
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SAMPLE_LATCH <= '1';
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(10, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(20, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(30, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(40, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(50, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(60, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(70, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(80, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(90, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(100, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(110, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(120, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(130, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(140, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(150, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(160, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(170, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(180, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(190, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(200, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(210, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(220, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(230, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(240, 8));
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wait for CLK_period;
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SAMPLE_DATA <= std_logic_vector(to_unsigned(250, 8));
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wait for CLK_period;
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SAMPLE_LATCH <= '0';
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wait;
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end process;
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END;
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