mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-01-19 07:00:33 +01:00
a4faeb28b0
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
166 lines
5.3 KiB
Plaintext
166 lines
5.3 KiB
Plaintext
CONFIG VCCAUX = 3.3;
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# Global FPGA clock
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NET "CLK" PERIOD = 62.5 ns HIGH 50%;
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# Constraints for SPI interface to MCU
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NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
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NET "MCU_MOSI" OFFSET = IN 2ns VALID 3ns BEFORE "MCU_SCK";
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NET "MCU_MISO" OFFSET = OUT 18.529ns VALID 10ns AFTER "MCU_SCK";
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NET "MCU_MISO" SLEW = FAST;
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# ADC constraints
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NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
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NET "REF_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "REF_SCLK";
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NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
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NET "PORT1_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT1_SCLK";
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NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
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NET "PORT2_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT2_SCLK";
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NET "PORT1_SCLK" SLEW = FAST;
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NET "PORT2_SCLK" SLEW = FAST;
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NET "REF_SCLK" SLEW = FAST;
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NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[4]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[3]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[2]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[1]" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[0]" IOSTANDARD = LVCMOS33;
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NET "LEDS[7]" IOSTANDARD = LVCMOS33;
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NET "LEDS[6]" IOSTANDARD = LVCMOS33;
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NET "LEDS[5]" IOSTANDARD = LVCMOS33;
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NET "LEDS[4]" IOSTANDARD = LVCMOS33;
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NET "LEDS[3]" IOSTANDARD = LVCMOS33;
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NET "LEDS[2]" IOSTANDARD = LVCMOS33;
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NET "LEDS[1]" IOSTANDARD = LVCMOS33;
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NET "LEDS[0]" IOSTANDARD = LVCMOS33;
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NET "AMP_PWDN" IOSTANDARD = LVCMOS33;
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NET "CLK" IOSTANDARD = LVCMOS33;
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NET "FILT_IN_C2" IOSTANDARD = LVCMOS33;
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NET "FILT_IN_C1" IOSTANDARD = LVCMOS33;
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NET "FILT_OUT_C2" IOSTANDARD = LVCMOS33;
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NET "FILT_OUT_C1" IOSTANDARD = LVCMOS33;
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NET "LO1_CE" IOSTANDARD = LVCMOS33;
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NET "LO1_LD" IOSTANDARD = LVCMOS33;
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NET "LO1_LE" IOSTANDARD = LVCMOS33;
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NET "LO1_CLK" IOSTANDARD = LVCMOS33;
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NET "LO1_MOSI" IOSTANDARD = LVCMOS33;
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NET "LO1_MUX" IOSTANDARD = LVCMOS33;
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NET "MCU_AUX1" IOSTANDARD = LVCMOS33;
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NET "LO1_RF_EN" IOSTANDARD = LVCMOS33;
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NET "SOURCE_RF_EN" IOSTANDARD = LVCMOS33;
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NET "SOURCE_MUX" IOSTANDARD = LVCMOS33;
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NET "SOURCE_LE" IOSTANDARD = LVCMOS33;
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NET "SOURCE_MOSI" IOSTANDARD = LVCMOS33;
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NET "SOURCE_LD" IOSTANDARD = LVCMOS33;
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NET "SOURCE_CLK" IOSTANDARD = LVCMOS33;
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NET "SOURCE_CE" IOSTANDARD = LVCMOS33;
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NET "RESET" IOSTANDARD = LVCMOS33;
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NET "REF_SDO" IOSTANDARD = LVCMOS33;
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NET "REF_SCLK" IOSTANDARD = LVCMOS33;
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NET "REF_CONVSTART" IOSTANDARD = LVCMOS33;
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NET "PORT2_SDO" IOSTANDARD = LVCMOS33;
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NET "PORT2_SCLK" IOSTANDARD = LVCMOS33;
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NET "PORT2_CONVSTART" IOSTANDARD = LVCMOS33;
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NET "PORT1_SDO" IOSTANDARD = LVCMOS33;
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NET "PORT1_SCLK" IOSTANDARD = LVCMOS33;
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NET "PORT1_CONVSTART" IOSTANDARD = LVCMOS33;
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NET "MCU_SCK" IOSTANDARD = LVCMOS33;
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NET "MCU_NSS" IOSTANDARD = LVCMOS33;
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NET "MCU_MISO" IOSTANDARD = LVCMOS33;
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NET "MCU_MOSI" IOSTANDARD = LVCMOS33;
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NET "MCU_INTR" IOSTANDARD = LVCMOS33;
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NET "MCU_AUX2" IOSTANDARD = LVCMOS33;
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NET "MCU_AUX3" IOSTANDARD = LVCMOS33;
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NET "TRIGGER_IN" IOSTANDARD = LVCMOS33;
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NET "TRIGGER_OUT" IOSTANDARD = LVCMOS33;
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NET "ATTENUATION[6]" LOC = P9;
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NET "ATTENUATION[5]" LOC = P10;
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NET "ATTENUATION[4]" LOC = P11;
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NET "ATTENUATION[3]" LOC = P12;
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NET "ATTENUATION[2]" LOC = P14;
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NET "ATTENUATION[1]" LOC = P15;
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NET "ATTENUATION[0]" LOC = P16;
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NET "LEDS[0]" LOC = P87;
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NET "LEDS[1]" LOC = P92;
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NET "LEDS[2]" LOC = P93;
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NET "LEDS[3]" LOC = P88;
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NET "LEDS[4]" LOC = P85;
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NET "LEDS[5]" LOC = P84;
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NET "LEDS[6]" LOC = P83;
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NET "LEDS[7]" LOC = P82;
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NET "AMP_PWDN" LOC = P8;
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NET "BAND_SELECT_HIGH" LOC = P21;
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NET "BAND_SELECT_LOW" LOC = P17;
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NET "CLK" LOC = P50;
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NET "FILT_IN_C1" LOC = P26;
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NET "FILT_IN_C2" LOC = P24;
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NET "FILT_OUT_C1" LOC = P22;
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NET "FILT_OUT_C2" LOC = P23;
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NET "LO1_CE" LOC = P45;
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NET "LO1_CLK" LOC = P48;
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NET "LO1_LD" LOC = P56;
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NET "LO1_LE" LOC = P46;
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NET "LO1_MOSI" LOC = P47;
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NET "LO1_MUX" LOC = P51;
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NET "LO1_RF_EN" LOC = P55;
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NET "MCU_AUX1" LOC = P78;
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NET "MCU_AUX2" LOC = P75;
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NET "MCU_AUX3" LOC = P74;
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NET "TRIGGER_IN" LOC = P80;
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NET "TRIGGER_OUT" LOC = P81;
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NET "MCU_INTR" LOC = P59;
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NET "MCU_MISO" LOC = P62;
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NET "MCU_MOSI" LOC = P61;
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NET "MCU_NSS" LOC = P67;
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NET "MCU_SCK" LOC = P66;
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NET "MCU_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
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# PlanAhead Generated physical constraints
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NET "PORT1_CONVSTART" LOC = P139;
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NET "PORT1_MIX1_EN" LOC = P141;
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NET "PORT1_MIX2_EN" LOC = P140;
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NET "PORT1_SCLK" LOC = P137;
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NET "PORT1_SDO" LOC = P138;
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NET "PORT1_SELECT" LOC = P142;
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NET "PORT2_CONVSTART" LOC = P44;
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NET "PORT2_MIX1_EN" LOC = P58;
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NET "PORT2_MIX2_EN" LOC = P57;
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NET "PORT2_SCLK" LOC = P41;
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NET "PORT2_SDO" LOC = P43;
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NET "PORT2_SELECT" LOC = P40;
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NET "PORT_SELECT1" LOC = P6;
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NET "PORT_SELECT2" LOC = P7;
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NET "REF_CONVSTART" LOC = P5;
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NET "REF_MIX1_EN" LOC = P144;
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NET "REF_MIX2_EN" LOC = P143;
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NET "REF_SCLK" LOC = P1;
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NET "REF_SDO" LOC = P2;
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NET "RESET" LOC = P79;
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NET "SOURCE_CE" LOC = P27;
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NET "SOURCE_CLK" LOC = P32;
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NET "SOURCE_LD" LOC = P35;
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NET "SOURCE_LE" LOC = P29;
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NET "SOURCE_MOSI" LOC = P30;
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NET "SOURCE_MUX" LOC = P33;
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NET "SOURCE_RF_EN" LOC = P34;
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# PlanAhead Generated IO constraints
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NET "BAND_SELECT_HIGH" IOSTANDARD = LVCMOS33;
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NET "BAND_SELECT_LOW" IOSTANDARD = LVCMOS33;
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NET "PORT1_MIX1_EN" IOSTANDARD = LVCMOS33;
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NET "PORT1_MIX2_EN" IOSTANDARD = LVCMOS33;
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NET "PORT1_SELECT" IOSTANDARD = LVCMOS33;
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NET "PORT2_MIX1_EN" IOSTANDARD = LVCMOS33;
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NET "PORT2_MIX2_EN" IOSTANDARD = LVCMOS33;
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NET "PORT2_SELECT" IOSTANDARD = LVCMOS33;
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NET "PORT_SELECT1" IOSTANDARD = LVCMOS33;
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NET "PORT_SELECT2" IOSTANDARD = LVCMOS33;
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NET "REF_MIX1_EN" IOSTANDARD = LVCMOS33;
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NET "REF_MIX2_EN" IOSTANDARD = LVCMOS33;
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