mirror of
https://github.com/jankae/LibreVNA.git
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1ea012aa57
Move CDS phase computation from per-point config storage to FPGA logic. The FPGA now computes the 180° phase shift internally (M/2) and loops twice per point when CDS is enabled. This keeps config memory at 96 bits instead of 112, avoiding BRAM overflow on the Spartan 6. FPGA changes: - Add CDS_ENABLED input to Sweep module (controlled via SPI register 6) - Compute source_phase = M/2 for 180° shift when cds_phase=1 - State machine loops through all stages twice per point when CDS enabled - RESULT_INDEX now includes cds_phase bit: stage[2:0] & point[11:0] & cds_phase Firmware changes: - Add FPGA::SetCDSEnabled() to control CDS via register 6 bit 11 - Update SamplingResult to include cdsPhase field (1 bit) - Simplify VNA.cpp: FPGA handles phase switching, MCU combines results Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com> |
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| .. | ||
| ipcore_dir | ||
| DFT.vhd | ||
| Flattop.dat | ||
| Hann.dat | ||
| Kaiser.dat | ||
| MAX2871.vhd | ||
| MCP33131.vhd | ||
| ResetDelay.vhd | ||
| Sampling.vhd | ||
| spi_slave.vhd | ||
| SPIConfig.vhd | ||
| Sweep.vhd | ||
| Synchronizer.vhd | ||
| Test_DFT.vhd | ||
| Test_MAX2871.vhd | ||
| Test_MCP33131.vhd | ||
| Test_PLL.vhd | ||
| Test_Sampling.vhd | ||
| Test_SinCos.vhd | ||
| Test_SPI.vhd | ||
| Test_SPICommands.vhd | ||
| Test_Window.vhd | ||
| Test_Windowing.vhd | ||
| top.bin | ||
| top.ucf | ||
| top.vhd | ||
| VNA.gise | ||
| VNA.xise | ||
| window.vhd | ||
| Windowing.vhd | ||