MAX2871Widget 0 0 1283 638 Form Registers Reference Input Manual Qt::Vertical 20 40 Calculated Frequencies Ref In: true true PFD: true true VCO: true true Out A: true true Out B: true true Reference Doubler Div-by-2 R-divider: 1023 R/N counter reset Qt::Vertical 20 40 Divider Settings Integer-N mode N: 16 65535 FRAC: 4095 M: 4095 4095 Phase: Charge Pump Linearity: Disabled 10% 20% 30% Test: Normal mode Long Reset mode Force source Force sink Current: 15 Polarity: Negative Positive High Impedance Output Divider: 1 2 4 8 16 32 64 128 Out B Path: Divided output Fundamental frequency Enable Out B Out B Power: -4 dBm -1 dBm +2 dBm +5 dBm Enable Out A Out A Power: -4 dBm -1 dBm +2 dBm +5 dBm Shutdown Shutdown VCO Shutdown VCO LDO Shutdown Reference Input Shutdown VCO Divider Shutdown Mode Shutdown PLL Lock Detect Speed: fPFD <= 32MHz fPFD > 32MHz Frac-N Int-N Function: 10ns 6ns Precision: Low Digital lock detect Analog lock detect High LD Pin: VCO VCO Band: 63 VAS Shutdown VAS temperature compensation VAS_DLY: 00 (when VAS_TEMP=0) Unknown Unknown 11 (when VAS_TEMP=1) Fundamental Feedback ADC Start Valid Code Mode: Disabled Temperature Reserved Reserved Tune pin Reserved Reserved Reserved Mixed Mute until lock Mute Delay Cycle Slip Mode Integer mode when F=0 Double buffer mode Clock Divider Mode: Mute until Lock Delay Fast-lock enabled Phase Adjustment mode Reserved Noise Mode: Low-noise Reserved Low-spur 1 Low-spur 2 MUX Pin: Three-state output DVDD DGND R-divider output N-divider/2 output Analog lock detect Digital lock detect Sync input Reserved Reserved Reserved Reserved Read SPI registers 6 Reserved Reserved Reserved Band Select: 1023 Clock Divider: 4095 SIUnitEdit QLineEdit

CustomWidgets/siunitedit.h