AD9913Widget 0 0 1263 635 Form Registers Reference Input Manual Calculated Frequencies Ref In: true true DDS Clock: true true Output: true true PLL Power down Reset Input Div-by-2 Range: Ref >5MHz Ref <5MHz Multiplication factor: 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 VCO mode: optimize for power optimize for performance Input Mode: Differential XTAL CMOS XTAL Output Div-by-2 false PLL lock Linear sweep Enable (aux. Accumulator) Enable Modulus No dwell Trigger mode: Edge State Destination: Frequency Word (FSK) Phase Word (PSK) Parameter lower limit: 429496729 Parameter upper limit: 429496729 Falling Delta Word: 429496729 Rising Delta Word: 429496729 Falling Ramp Rate: 65535 Rising Ramp Rate: 65535 DDS Frequency tuning word: 429496729 Phase Offset: 16384 Interface Disable SYNC clock Load SSR@IO_Update Autoclear Phase Accumulator Autoclear Auxiliary Accumulator Format: MSB first LSB first Power down External power down mode Power down Input Power down DAC Power down digital Mixed Clear Phase Accumulator Clear Auxiliary Accumulator Direct switch mode Match pipeline delays Output Output type: Cosine Sine DAC Fullscale: 1023 DC Output Profiles Use internal profile Internal Profile: Profile 0/Sweep Off Profile 1/Ramp up Profile 2/Ramp down Profile 3/Bidirectional ramp Profile 4/Sweep Off Profile 5/Ramp up Profile 6/Ramp down Profile 7/Bidirectional ramp 16384 429496729 Frequency Word: 16384 3: 429496729 16384 16384 16384 16384 6: 1: 16384 429496729 429496729 16384 2: 429496729 4: 5: 7: 429496729 0: 429496729 Phase: 429496729 SIUnitEdit QLineEdit

CustomWidgets/siunitedit.h