jankae/LibreVNA
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697 commits 11 branches 20 tags 313 MiB
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26 commits

Author SHA1 Message Date
Jan Käberich 0c17288ece SA/GEN integration tests + bugfixes 2022-11-20 20:48:36 +01:00
Jan Käberich df8fa25935 Increase settling time for PLLs 2022-11-19 16:26:38 +01:00
Jan Käberich 73e26a25c4 WIP: synchronization 2022-08-08 18:08:40 +02:00
Jan Käberich 58918f81c1 WIP: device synchronization 2022-08-07 03:01:22 +02:00
Jan Käberich 047f6ce981 more flexible USB protocol for VNA settings/measurements 2022-08-06 16:22:12 +02:00
Jan Käberich 8492b38936 Zerospan mode for spectrum analyzer mode 2022-06-26 22:53:12 +02:00
Jan Käberich 51396491f8 Fix LO1 compensation during signal ID steps 2022-06-07 16:14:08 +02:00
Jan Käberich c6ef075f4f split device info and status protocol messages 2022-04-03 20:26:30 +02:00
Jan Käberich 37d8474260 Added stages to FPGA protocol 2022-04-01 23:01:22 +02:00
Jan Käberich 5d8efd4336 user selectable IF frequencies 2022-01-15 16:11:33 +01:00
Jan Käberich 71b095cf2e Fix pointNum in SA result for DFT mode with narrow spans 2021-11-11 22:09:45 +01:00
Jan Käberich 938f444c73 TCXO offset calibration 2021-05-01 18:34:53 +02:00
Jan Käberich e3f072b307 display error flags in statusbar (overload/unlock/unlevel) 2021-02-11 22:49:47 +01:00
Jan Käberich 00f0de43f2 Timeout handling in FPGA communication (better recovery from missing reference) 2020-12-15 18:03:29 +01:00
Jan Käberich 7b41f10604 Bugfix: wrong sign for tracking generator offset 2020-11-21 12:02:27 +01:00
Jan Käberich 5b771e2a86 Tracking generator with offset + incomplete automatic source/receiver calibration 2020-11-18 19:19:29 +01:00
Jan Käberich 026fffd588 Working source and receiver calibration 2020-11-17 23:03:13 +01:00
Jan Käberich 3055564a27 signal ID improved 2020-11-14 23:53:55 +01:00
Jan Käberich a2389fca13 Protocol adjustment + exposing settings for DFT 2020-11-08 14:38:31 +01:00
Jan Käberich ce475fa042 Basic DFT spectrum analysis working 2020-11-08 14:38:31 +01:00
Jan Käberich f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich 6bc6b1d202 Speed improvements 2020-10-03 21:56:09 +02:00
Jan Käberich 926392e5b9 Bugfixes and speed improvements 2020-09-26 23:34:31 +02:00
Jan Käberich 57b4ebfb26 mitigation for peaks caused by limited fractional divider in PLLs 2020-09-20 10:13:06 +02:00
Jan Käberich fc3ce7a828 Improved spectrum analyzer mode 
- Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency
- Added FPGA settings for selectable ADC samplerate
- Additional measurement with different ADC samplerate when signal ID is on to remove ADC images
 2020-09-17 19:54:03 +02:00
Jan Käberich 38e73365df proof-of-concept spectrum analyzer mode 2020-09-17 15:51:20 +02:00