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https://github.com/jankae/LibreVNA.git
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Reference control added
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parent
6960498fcb
commit
e266d37b96
13 changed files with 272 additions and 143 deletions
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@ -36,6 +36,9 @@ static uint16_t IFTableIndexCnt = 0;
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static constexpr uint32_t BandSwitchFrequency = 25000000;
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static uint32_t extOutFreq = 0;
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static bool extRefInUse = false;
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using namespace VNAHAL;
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static void HaltedCallback() {
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@ -129,6 +132,10 @@ bool VNA::Init() {
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Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::B));
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extRefInUse = 0;
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extOutFreq = 0;
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Si5351.Disable(SiChannel::ReferenceOut);
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// Both MAX2871 get a 100MHz reference
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Si5351.SetCLK(SiChannel::Source, 100000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Source);
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@ -137,10 +144,6 @@ bool VNA::Init() {
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// 16MHz FPGA clock
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Si5351.SetCLK(SiChannel::FPGA, 16000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::FPGA);
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// TODO reference settings controllable through USB
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// // 10 MHz external reference clock
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// Si5351.SetCLK(6, 10000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA8);
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// Si5351.Enable(6);
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// Generate second LO with Si5351
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Si5351.SetCLK(SiChannel::Port1LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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@ -410,3 +413,80 @@ bool VNA::GetTemps(uint8_t *source, uint8_t *lo) {
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FPGA::SetMode(FPGA::Mode::FPGA);
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return true;
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}
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void VNA::fillDeviceInfo(Protocol::DeviceInfo *info) {
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// read PLL temperatures
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uint8_t tempSource, tempLO;
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VNA::GetTemps(&tempSource, &tempLO);
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LOG_INFO("PLL temperatures: %u/%u", tempSource, tempLO);
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// Read ADC min/max
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auto limits = FPGA::GetADCLimits();
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LOG_INFO("ADC limits: P1: %d/%d P2: %d/%d R: %d/%d",
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limits.P1min, limits.P1max, limits.P2min, limits.P2max,
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limits.Rmin, limits.Rmax);
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#define ADC_LIMIT 30000
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// Set VNA related member of info struct
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if(limits.P1min < -ADC_LIMIT || limits.P1max > ADC_LIMIT
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|| limits.P2min < -ADC_LIMIT || limits.P2max > ADC_LIMIT
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|| limits.Rmin < -ADC_LIMIT || limits.Rmax > ADC_LIMIT) {
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info->ADC_overload = true;
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} else {
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info->ADC_overload = false;
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}
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auto status = FPGA::GetStatus();
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info->LO1_locked = (status & (int) FPGA::Interrupt::LO1Unlock) ? 0 : 1;
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info->source_locked = (status & (int) FPGA::Interrupt::SourceUnlock) ? 0 : 1;
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info->extRefAvailable = Ref::available();
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info->extRefInUse = extRefInUse;
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info->temperatures.LO1 = tempLO;
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info->temperatures.source = tempSource;
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info->temperatures.MCU = 0;
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FPGA::ResetADCLimits();
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}
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bool VNA::Ref::available() {
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return Si5351.ExtCLKAvailable();
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}
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bool VNA::Ref::applySettings(Protocol::ReferenceSettings s) {
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if(extOutFreq != s.ExtRefOuputFreq) {
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extOutFreq = s.ExtRefOuputFreq;
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if(extOutFreq == 0) {
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Si5351.Disable(SiChannel::ReferenceOut);
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LOG_INFO("External reference output disabled");
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} else {
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Si5351.SetCLK(SiChannel::ReferenceOut, extOutFreq, Si5351C::PLL::A);
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Si5351.Enable(SiChannel::ReferenceOut);
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LOG_INFO("External reference output set to %luHz", extOutFreq);
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}
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}
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bool useExternal = s.UseExternalRef || (s.AutomaticSwitch && Ref::available());
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if(useExternal != extRefInUse) {
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// switch between internal and external reference
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extRefInUse = useExternal;
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if(extRefInUse) {
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if(!Ref::available()) {
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LOG_WARN("Forced switch to external reference but no signal detected");
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}
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Si5351.ConfigureCLKIn(10000000);
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Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::CLKIN);
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Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::CLKIN);
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LOG_INFO("Switched to external reference");
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FPGA::Enable(FPGA::Periphery::ExtRefLED);
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} else {
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Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::XTAL);
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Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::XTAL);
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LOG_INFO("Switched to internal reference");
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FPGA::Disable(FPGA::Periphery::ExtRefLED);
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}
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}
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constexpr uint32_t lock_timeout = 10;
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uint32_t start = HAL_GetTick();
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while(!Si5351.Locked(Si5351C::PLL::A) || !Si5351.Locked(Si5351C::PLL::A)) {
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if(HAL_GetTick() - start > lock_timeout) {
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LOG_ERR("Clock distributor PLLs failed to lock");
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return false;
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}
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}
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return false;
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}
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