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Increase settling time for PLLs

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Jan Käberich 2022-11-19 16:26:38 +01:00
parent 32e2a4d96d
commit df8fa25935
3 changed files with 3 additions and 3 deletions
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2
Software/VNA_embedded/Application/SpectrumAnalyzer.cpp
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@ -172,7 +172,7 @@ static void StartNextSample() {
// Configure the sampling in the FPGA
FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator,
trackingFreq, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0,
trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0,
FPGA::LowpassFilter::Auto);
FPGA::StartSweep();