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Increase settling time for PLLs

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This commit is contained in:
Jan Käberich 2022-11-19 16:26:38 +01:00
parent 32e2a4d96d
commit df8fa25935
3 changed files with 3 additions and 3 deletions
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2
Software/VNA_embedded/Application/Manual.cpp
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@ -54,7 +54,7 @@ void Manual::Setup(Protocol::ManualControlV1 m) {
// Configure single sweep point
FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(),
LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us20,
LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us60,
FPGA::Samples::SPPRegister, 0,
(FPGA::LowpassFilter) m.SourceHighLowpass);