Experimental feature: only excite one port when other traces are paused

This commit is contained in:
Jan Käberich 2020-09-15 23:22:08 +02:00
parent 44124bc09e
commit de8761545d
18 changed files with 130 additions and 40 deletions

View file

@ -178,8 +178,7 @@ void App_Start() {
case Protocol::PacketType::SweepSettings:
LOG_INFO("New settings received");
settings = packet.settings;
VNA::ConfigureSweep(settings, VNACallback);
sweepActive = true;
sweepActive = VNA::ConfigureSweep(settings, VNACallback);
lastNewPoint = HAL_GetTick();
Communication::SendWithoutPayload(Protocol::PacketType::Ack);
break;

View file

@ -174,6 +174,8 @@ static Protocol::SweepSettings DecodeSweepSettings(uint8_t *buf) {
e.get<uint16_t>(d.points);
e.get<uint32_t>(d.if_bandwidth);
e.get<int16_t>(d.cdbm_excitation);
d.excitePort1 = e.getBits(1);
d.excitePort2 = e.getBits(1);
return d;
}
static int16_t EncodeSweepSettings(Protocol::SweepSettings d, uint8_t *buf,
@ -184,6 +186,8 @@ static int16_t EncodeSweepSettings(Protocol::SweepSettings d, uint8_t *buf,
e.add<uint16_t>(d.points);
e.add<uint32_t>(d.if_bandwidth);
e.add<int16_t>(d.cdbm_excitation);
e.addBits(d.excitePort1, 1);
e.addBits(d.excitePort2, 1);
return e.getSize();
}

View file

@ -21,6 +21,8 @@ using SweepSettings = struct _sweepSettings {
uint16_t points;
uint32_t if_bandwidth;
int16_t cdbm_excitation; // in 1/100 dbm
uint8_t excitePort1:1;
uint8_t excitePort2:1;
};
using ReferenceSettings = struct _referenceSettings {

View file

@ -82,9 +82,9 @@ static void ReadComplete(FPGA::SamplingResult result) {
auto ref = std::complex<float>(result.RefI, result.RefQ);
auto port1 = port1_raw / ref;
auto port2 = port2_raw / ref;
data.pointNum = pointCnt;
data.frequency = settings.f_start + (settings.f_stop - settings.f_start) * pointCnt / (settings.points - 1);
if(excitingPort1) {
data.pointNum = pointCnt;
data.frequency = settings.f_start + (settings.f_stop - settings.f_start) * pointCnt / (settings.points - 1);
data.real_S11 = port1.real();
data.imag_S11 = port1.imag();
data.real_S21 = port2.real();
@ -94,6 +94,19 @@ static void ReadComplete(FPGA::SamplingResult result) {
data.imag_S12 = port1.imag();
data.real_S22 = port2.real();
data.imag_S22 = port2.imag();
}
// figure out whether this sweep point is complete and which port gets excited next
bool pointComplete = false;
if(settings.excitePort1 == 1 && settings.excitePort2 == 1) {
// point is complete when port 2 was active
pointComplete = !excitingPort1;
// next measurement will be from other port
excitingPort1 = !excitingPort1;
} else {
// only one port active, point is complete after every measurement
pointComplete = true;
}
if(pointComplete) {
if (sweepCallback) {
sweepCallback(data);
}
@ -102,10 +115,8 @@ static void ReadComplete(FPGA::SamplingResult result) {
// reached end of sweep, start again
pointCnt = 0;
IFTableIndexCnt = 0;
// FPGA::StartSweep();
}
}
excitingPort1 = !excitingPort1;
} else {
// Manual control mode, simply pass on raw result
if(statusCallback) {
@ -218,6 +229,11 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
// was used in manual mode last, do full initialization before starting sweep
VNA::Init();
}
if(s.excitePort1 == 0 && s.excitePort2 == 0) {
// both ports disabled, set to idle
SetIdle();
return false;
}
sweepCallback = cb;
settings = s;
// Abort possible active sweep first
@ -316,7 +332,7 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
}
LO1.SetFrequency(freq + used_IF);
FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us540,
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20,
FPGA::Samples::SPPRegister, needs_halt);
last_lowband = lowband;
}
@ -332,10 +348,11 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
FPGA::Enable(FPGA::Periphery::SourceRF);
FPGA::Enable(FPGA::Periphery::LO1Chip);
FPGA::Enable(FPGA::Periphery::LO1RF);
FPGA::Enable(FPGA::Periphery::ExcitePort1);
FPGA::Enable(FPGA::Periphery::ExcitePort2);
FPGA::Enable(FPGA::Periphery::ExcitePort1, s.excitePort1);
FPGA::Enable(FPGA::Periphery::ExcitePort2, s.excitePort2);
pointCnt = 0;
excitingPort1 = true;
// starting port depends on whether port 1 is active in sweep
excitingPort1 = s.excitePort1;
IFTableIndexCnt = 0;
// Start the sweep
FPGA::StartSweep();
@ -461,7 +478,10 @@ bool VNA::Ref::applySettings(Protocol::ReferenceSettings s) {
LOG_INFO("External reference output set to %luHz", extOutFreq);
}
}
bool useExternal = s.UseExternalRef || (s.AutomaticSwitch && Ref::available());
bool useExternal = s.UseExternalRef;
if (s.AutomaticSwitch) {
useExternal = Ref::available();
}
if(useExternal != extRefInUse) {
// switch between internal and external reference
extRefInUse = useExternal;

View file

@ -10,6 +10,7 @@ using SweepCallback = void(*)(Protocol::Datapoint);
using StatusCallback = void(*)(FPGA::SamplingResult);
bool Init();
// returns whether the sweep is actually started
bool ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb);
bool ConfigureManual(Protocol::ManualControl m, StatusCallback cb);
bool ConfigureGenerator(Protocol::GeneratorSettings g);