mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-04 22:17:31 +00:00
Basic DFT spectrum analysis working
This commit is contained in:
Jan Käberich
parent
f889ec854b
commit
ce475fa042
27 changed files with 1313 additions and 563 deletions
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@ -12,6 +12,7 @@
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static FPGA::HaltedCallback halted_cb;
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static uint16_t SysCtrlReg = 0x0000;
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static uint16_t ISRMaskReg = 0x0000;
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static uint32_t ADC_samplerate;
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using namespace FPGAHAL;
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@ -27,6 +28,9 @@ void FPGA::WriteRegister(FPGA::Reg reg, uint16_t value) {
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 4, 100);
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High(CS);
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if(reg == Reg::ADCPrescaler) {
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ADC_samplerate = Clockrate / value;
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}
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}
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bool FPGA::Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size) {
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@ -371,6 +375,23 @@ void FPGA::ResumeHaltedSweep() {
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High(CS);
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}
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void FPGA::SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing) {
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// see FPGA protocol for formulas
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uint16_t firstBin = f_firstBin * (1ULL << 16) / ADC_samplerate;
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uint16_t binSpacing = f_binSpacing * (1ULL << 24) / ADC_samplerate;
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WriteRegister(Reg::DFTFirstBin, firstBin);
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WriteRegister(Reg::DFTFreqSpacing, binSpacing);
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}
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void FPGA::StopDFT() {
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DisableInterrupt(Interrupt::DFTReady);
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}
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void FPGA::StartDFT() {
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StopDFT();
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EnableInterrupt(Interrupt::DFTReady);
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}
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FPGA::DFTResult FPGA::ReadDFTResult() {
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uint8_t cmd[2] = {0xA0, 0x00};
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uint8_t recv[24];
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@ -7,6 +7,7 @@ namespace FPGA {
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static constexpr uint16_t MaxPoints = 4501;
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static constexpr uint16_t DFTbins = 64;
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static constexpr uint32_t Clockrate = 102400000UL;
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enum class Reg {
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InterruptMask = 0x00,
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@ -23,8 +24,6 @@ enum class Reg {
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MAX2871Def3MSB = 0x0D,
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MAX2871Def4LSB = 0x0E,
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MAX2871Def4MSB = 0x0F,
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DFTSamples = 0x10,
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DFTWindowInc = 0x11,
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DFTFirstBin = 0x12,
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DFTFreqSpacing = 0x13,
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};
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@ -124,6 +123,9 @@ void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uin
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uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
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using ReadCallback = void(*)(const SamplingResult &result);
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bool InitiateSampleRead(ReadCallback cb);
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void SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing);
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void StopDFT();
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void StartDFT();
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DFTResult ReadDFTResult();
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ADCLimits GetADCLimits();
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void ResetADCLimits();
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@ -315,29 +315,31 @@ void Si5351C::FindOptimalDivider(uint32_t f_pll, uint32_t f, uint32_t &P1,
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// see https://www.silabs.com/documents/public/application-notes/AN619.pdf (page 3/6)
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uint32_t a = f_pll / f;
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int32_t f_rem = f_pll - f * a;
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uint32_t best_b, best_c;
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uint32_t best_deviation = UINT32_MAX;
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for (uint32_t c = (1UL << 20) - 1; c >= (1UL << 19); c--) {
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uint32_t guess_b = (uint64_t) f_rem * c / f;
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for (uint32_t b = guess_b; b <= guess_b + 1; b++) {
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int32_t f_div = (uint64_t) f * b / c;
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uint32_t deviation = abs(f_rem - f_div);
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if (deviation < best_deviation) {
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best_b = b;
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best_c = c;
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best_deviation = deviation;
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if (deviation == 0) {
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break;
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}
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}
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}
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if (best_deviation == 0) {
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break;
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}
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}
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LOG_DEBUG(
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"Optimal divider for %luHz/%luHz is: a=%lu, b=%lu, c=%lu (%luHz deviation)",
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f_pll, f, a, best_b, best_c, best_deviation);
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// always using the highest modulus divider results in less than 1Hz deviation for all frequencies, that is good enough
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uint32_t best_c = (1UL << 20) - 1;
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uint32_t best_b = (uint64_t) f_rem * best_c / f;
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// uint32_t best_deviation = UINT32_MAX;
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// for (uint32_t c = (1UL << 20) - 1; c >= (1UL << 19); c--) {
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// uint32_t guess_b = (uint64_t) f_rem * c / f;
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// for (uint32_t b = guess_b; b <= guess_b + 1; b++) {
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// int32_t f_div = (uint64_t) f * b / c;
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// uint32_t deviation = abs(f_rem - f_div);
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// if (deviation < best_deviation) {
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// best_b = b;
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// best_c = c;
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// best_deviation = deviation;
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// if (deviation <= 3) {
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// break;
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// }
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// }
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// }
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// if (best_deviation <= 3) {
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// break;
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// }
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// }
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// LOG_DEBUG(
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// "Optimal divider for %luHz/%luHz is: a=%lu, b=%lu, c=%lu (%luHz deviation)",
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// f_pll, f, a, best_b, best_c, best_deviation);
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// convert to Si5351C parameters
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uint32_t floor = 128 * best_b / best_c;
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P1 = 128 * a + floor - 512;
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@ -131,10 +131,6 @@ bool HW::Init() {
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// Set phase increment according to
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::DFTphaseInc);
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// Enable new data and sweep halt interrupt
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FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
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FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
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Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
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// Initialize PLLs and build VCO maps
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@ -2,6 +2,7 @@
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#include <cstdint>
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#include "Protocol.hpp"
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#include "FPGA/FPGA.hpp"
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#define USE_DEBUG_PINS
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@ -31,10 +32,9 @@ static constexpr uint32_t LO1_minFreq = 25000000;
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static constexpr uint32_t MaxSamples = 130944;
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static constexpr uint32_t MinSamples = 16;
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static constexpr uint32_t PLLRef = 100000000;
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static constexpr uint16_t MaxPoints = 4501;
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static constexpr uint8_t ADCprescaler = 102400000UL / ADCSamplerate;
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static_assert(ADCprescaler * ADCSamplerate == 102400000UL, "ADCSamplerate can not be reached exactly");
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static constexpr uint8_t ADCprescaler = FPGA::Clockrate / ADCSamplerate;
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static_assert(ADCprescaler * ADCSamplerate == FPGA::Clockrate, "ADCSamplerate can not be reached exactly");
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static constexpr uint16_t DFTphaseInc = 4096 * IF2 / ADCSamplerate;
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static_assert(DFTphaseInc * ADCSamplerate == 4096 * IF2, "DFT can not be computed for 2.IF");
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@ -43,7 +43,7 @@ static constexpr Protocol::DeviceLimits Limits = {
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.maxFreq = 6000000000,
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.minIFBW = ADCSamplerate / MaxSamples,
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.maxIFBW = ADCSamplerate / MinSamples,
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.maxPoints = MaxPoints,
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.maxPoints = FPGA::MaxPoints,
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.cdbm_min = -4000,
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.cdbm_max = 0,
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.minRBW = (uint32_t) (ADCSamplerate * 2.23f / MaxSamples),
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@ -73,6 +73,9 @@ void Manual::Setup(Protocol::ManualControl m) {
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FPGA::Enable(FPGA::Periphery::ExcitePort2, m.PortSwitch == 1);
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FPGA::Enable(FPGA::Periphery::PortSwitch);
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// Enable new data and sweep halt interrupt
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FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
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active = true;
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FPGA::StartSweep();
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}
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@ -11,6 +11,8 @@
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#define LOG_MODULE "SA"
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#include "Log.h"
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using namespace HWHAL;
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static Protocol::SpectrumAnalyzerSettings s;
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static uint32_t pointCnt;
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static uint32_t points;
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@ -21,10 +23,11 @@ static Protocol::PacketInfo p;
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static bool active = false;
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static uint32_t lastLO2;
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static uint32_t actualRBW;
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static bool usingDFT;
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static uint16_t DFTpoints;
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static bool negativeDFT; // if true, a positive frequency shift at input results in a negative shift at the 2.IF. Handle DFT accordingly
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static float port1Measurement, port2Measurement;
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using namespace HWHAL;
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static float port1Measurement[FPGA::DFTbins], port2Measurement[FPGA::DFTbins];
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static void StartNextSample() {
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * pointCnt / (points - 1);
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@ -34,16 +37,20 @@ static void StartNextSample() {
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case 0:
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default:
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// reset minimum amplitudes in first signal ID step
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port1Measurement = std::numeric_limits<float>::max();
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port2Measurement = std::numeric_limits<float>::max();
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for (uint16_t i = 0; i < DFTpoints; i++) {
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port1Measurement[i] = std::numeric_limits<float>::max();
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port2Measurement[i] = std::numeric_limits<float>::max();
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}
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// Use default LO frequencies
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 - HW::IF2;
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 112);
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1120);
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negativeDFT = true;
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break;
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case 1:
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LO2freq = HW::IF1 - HW::IF2;
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negativeDFT = false;
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// Shift first LO to other side
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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@ -59,13 +66,15 @@ static void StartNextSample() {
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signalIDstep++;
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/* no break */
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case 2:
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// Shift both LOs to other side
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// Shift second LOs to other side
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 + HW::IF2;
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negativeDFT = false;
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break;
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case 3:
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// Shift both LO to other side
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LO2freq = HW::IF1 + HW::IF2;
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// Shift second LO to other side
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negativeDFT = true;
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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// frequency is high enough to shift 1.LO below measurement frequency
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@ -81,6 +90,7 @@ static void StartNextSample() {
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/* no break */
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case 4:
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// Use default frequencies with different ADC samplerate to remove images in final IF
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negativeDFT = true;
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 - HW::IF2;
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 120);
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@ -96,6 +106,17 @@ static void StartNextSample() {
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Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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lastLO2 = LO2freq;
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}
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if (usingDFT) {
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uint32_t spacing = (s.f_stop - s.f_start) / (points - 1);
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uint32_t start = HW::IF2;
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if(negativeDFT) {
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// needs to look below the start frequency, shift start
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start -= spacing * (DFTpoints - 1);
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}
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FPGA::SetupDFT(start, spacing);
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FPGA::StartDFT();
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}
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// Configure the sampling in the FPGA
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FPGA::WriteSweepConfig(0, 0, Source.GetRegisters(), LO1.GetRegisters(), 0,
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0, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0,
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@ -111,9 +132,6 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
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s = settings;
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HW::SetMode(HW::Mode::SA);
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FPGA::SetMode(FPGA::Mode::FPGA);
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FPGA::DisableInterrupt(FPGA::Interrupt::NewData);
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FPGA::DisableInterrupt(FPGA::Interrupt::SweepHalted);
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FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
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// in almost all cases a full sweep requires more points than the FPGA can handle at a time
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// individually start each point and do the sweep in the uC
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FPGA::SetNumberOfPoints(1);
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@ -148,12 +166,17 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
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FPGA::Enable(FPGA::Periphery::Port1Mixer);
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FPGA::Enable(FPGA::Periphery::Port2Mixer);
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// Configure DFT
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LOG_INFO("DFT samples: %lu", sampleNum);
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FPGA::WriteRegister(FPGA::Reg::DFTSamples, sampleNum - 1);
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FPGA::WriteRegister(FPGA::Reg::DFTWindowInc, 65536 / sampleNum);
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FPGA::WriteRegister(FPGA::Reg::DFTFirstBin, 17920);
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FPGA::WriteRegister(FPGA::Reg::DFTFreqSpacing, 1147);
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// automatically select DFT mode for lower RBWs
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usingDFT = actualRBW <= 1000;
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if (usingDFT) {
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DFTpoints = FPGA::DFTbins; // use full DFT in FPGA
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FPGA::DisableInterrupt(FPGA::Interrupt::NewData);
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} else {
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DFTpoints = 1; // can only measure one point at a time
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FPGA::StopDFT();
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FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
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}
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lastLO2 = 0;
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active = true;
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@ -166,26 +189,39 @@ bool SA::MeasurementDone(const FPGA::SamplingResult &result) {
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}
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FPGA::AbortSweep();
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uint16_t i=0;
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while(FPGA::GetStatus() & (uint16_t) FPGA::Interrupt::DFTReady) {
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auto dft = FPGA::ReadDFTResult();
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dft.P1 /= sampleNum;
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dft.P2 /= sampleNum;
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LOG_INFO("DFT %d: %lu, %lu", i, (uint32_t) dft.P1, (uint32_t) dft.P2);
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Log_Flush();
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i++;
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}
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FPGA::DisableInterrupt(FPGA::Interrupt::DFTReady);
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FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
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for(uint16_t i=0;i<DFTpoints;i++) {
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float port1, port2;
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if (usingDFT) {
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// use DFT result
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auto dft = FPGA::ReadDFTResult();
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port1 = dft.P1;
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port2 = dft.P2;
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} else {
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port1 = abs(std::complex<float>(result.P1I, result.P1Q));
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port2 = abs(std::complex<float>(result.P2I, result.P2Q));
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}
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port1 /= sampleNum;
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port2 /= sampleNum;
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float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum;
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float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum;
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if(port1 < port1Measurement) {
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port1Measurement = port1;
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uint16_t index = i;
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if (negativeDFT) {
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// bin order is reversed
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index = DFTpoints - i - 1;
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}
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if(port1 < port1Measurement[index]) {
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port1Measurement[index] = port1;
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}
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if(port2 < port2Measurement[index]) {
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port2Measurement[index] = port2;
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}
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}
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if(port2 < port2Measurement) {
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port2Measurement = port2;
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if (usingDFT) {
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FPGA::StopDFT();
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// will be started again in StartNextSample
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}
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// trigger work function
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return true;
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}
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@ -196,74 +232,76 @@ void SA::Work() {
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}
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if(!s.SignalID || signalIDstep >= 4) {
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// this measurement point is done, handle result according to detector
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uint16_t binIndex = pointCnt / binSize;
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uint32_t pointInBin = pointCnt % binSize;
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bool lastPointInBin = pointInBin >= binSize - 1;
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auto det = (Detector) s.Detector;
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if(det == Detector::Normal) {
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det = binIndex & 0x01 ? Detector::PosPeak : Detector::NegPeak;
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}
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switch(det) {
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case Detector::PosPeak:
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if(pointInBin == 0) {
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p.spectrumResult.port1 = std::numeric_limits<float>::min();
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p.spectrumResult.port2 = std::numeric_limits<float>::min();
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for(uint16_t i=0;i<DFTpoints;i++) {
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uint16_t binIndex = (pointCnt + i) / binSize;
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uint32_t pointInBin = (pointCnt + i) % binSize;
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bool lastPointInBin = pointInBin >= binSize - 1;
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auto det = (Detector) s.Detector;
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if(det == Detector::Normal) {
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det = binIndex & 0x01 ? Detector::PosPeak : Detector::NegPeak;
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}
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if(port1Measurement > p.spectrumResult.port1) {
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p.spectrumResult.port1 = port1Measurement;
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switch(det) {
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case Detector::PosPeak:
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if(pointInBin == 0) {
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p.spectrumResult.port1 = std::numeric_limits<float>::min();
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p.spectrumResult.port2 = std::numeric_limits<float>::min();
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}
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if(port1Measurement[i] > p.spectrumResult.port1) {
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p.spectrumResult.port1 = port1Measurement[i];
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}
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if(port2Measurement[i] > p.spectrumResult.port2) {
|
||||
p.spectrumResult.port2 = port2Measurement[i];
|
||||
}
|
||||
break;
|
||||
case Detector::NegPeak:
|
||||
if(pointInBin == 0) {
|
||||
p.spectrumResult.port1 = std::numeric_limits<float>::max();
|
||||
p.spectrumResult.port2 = std::numeric_limits<float>::max();
|
||||
}
|
||||
if(port1Measurement[i] < p.spectrumResult.port1) {
|
||||
p.spectrumResult.port1 = port1Measurement[i];
|
||||
}
|
||||
if(port2Measurement[i] < p.spectrumResult.port2) {
|
||||
p.spectrumResult.port2 = port2Measurement[i];
|
||||
}
|
||||
break;
|
||||
case Detector::Sample:
|
||||
if(pointInBin <= binSize / 2) {
|
||||
// still in first half of bin, simply overwrite
|
||||
p.spectrumResult.port1 = port1Measurement[i];
|
||||
p.spectrumResult.port2 = port2Measurement[i];
|
||||
}
|
||||
break;
|
||||
case Detector::Average:
|
||||
if(pointInBin == 0) {
|
||||
p.spectrumResult.port1 = 0;
|
||||
p.spectrumResult.port2 = 0;
|
||||
}
|
||||
p.spectrumResult.port1 += port1Measurement[i];
|
||||
p.spectrumResult.port2 += port2Measurement[i];
|
||||
if(lastPointInBin) {
|
||||
// calculate average
|
||||
p.spectrumResult.port1 /= binSize;
|
||||
p.spectrumResult.port2 /= binSize;
|
||||
}
|
||||
break;
|
||||
case Detector::Normal:
|
||||
// nothing to do, normal detector handled by PosPeak or NegPeak in each sample
|
||||
break;
|
||||
}
|
||||
if(port2Measurement > p.spectrumResult.port2) {
|
||||
p.spectrumResult.port2 = port2Measurement;
|
||||
}
|
||||
break;
|
||||
case Detector::NegPeak:
|
||||
if(pointInBin == 0) {
|
||||
p.spectrumResult.port1 = std::numeric_limits<float>::max();
|
||||
p.spectrumResult.port2 = std::numeric_limits<float>::max();
|
||||
}
|
||||
if(port1Measurement < p.spectrumResult.port1) {
|
||||
p.spectrumResult.port1 = port1Measurement;
|
||||
}
|
||||
if(port2Measurement < p.spectrumResult.port2) {
|
||||
p.spectrumResult.port2 = port2Measurement;
|
||||
}
|
||||
break;
|
||||
case Detector::Sample:
|
||||
if(pointInBin <= binSize / 2) {
|
||||
// still in first half of bin, simply overwrite
|
||||
p.spectrumResult.port1 = port1Measurement;
|
||||
p.spectrumResult.port2 = port2Measurement;
|
||||
}
|
||||
break;
|
||||
case Detector::Average:
|
||||
if(pointInBin == 0) {
|
||||
p.spectrumResult.port1 = 0;
|
||||
p.spectrumResult.port2 = 0;
|
||||
}
|
||||
p.spectrumResult.port1 += port1Measurement;
|
||||
p.spectrumResult.port2 += port2Measurement;
|
||||
if(lastPointInBin) {
|
||||
// calculate average
|
||||
p.spectrumResult.port1 /= binSize;
|
||||
p.spectrumResult.port2 /= binSize;
|
||||
// Send result to application
|
||||
p.type = Protocol::PacketType::SpectrumAnalyzerResult;
|
||||
// measurements are already up to date, fill remaining fields
|
||||
p.spectrumResult.pointNum = binIndex;
|
||||
p.spectrumResult.frequency = s.f_start + (s.f_stop - s.f_start) * binIndex / (s.pointNum - 1);
|
||||
Communication::Send(p);
|
||||
}
|
||||
break;
|
||||
case Detector::Normal:
|
||||
// nothing to do, normal detector handled by PosPeak or NegPeak in each sample
|
||||
break;
|
||||
}
|
||||
if(lastPointInBin) {
|
||||
// Send result to application
|
||||
p.type = Protocol::PacketType::SpectrumAnalyzerResult;
|
||||
// measurements are already up to date, fill remaining fields
|
||||
p.spectrumResult.pointNum = binIndex;
|
||||
p.spectrumResult.frequency = s.f_start + (s.f_stop - s.f_start) * binIndex / (s.pointNum - 1);
|
||||
Communication::Send(p);
|
||||
}
|
||||
// setup for next step
|
||||
signalIDstep = 0;
|
||||
if(pointCnt < points - 1) {
|
||||
pointCnt++;
|
||||
if(pointCnt < points - DFTpoints) {
|
||||
pointCnt += DFTpoints;
|
||||
} else {
|
||||
pointCnt = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -187,6 +187,9 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
|
|||
IFTableIndexCnt = 0;
|
||||
adcShifted = false;
|
||||
active = true;
|
||||
// Enable new data and sweep halt interrupt
|
||||
FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
|
||||
FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
|
||||
// Start the sweep
|
||||
FPGA::StartSweep();
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue