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https://github.com/jankae/LibreVNA.git
synced 2026-04-06 06:53:37 +00:00
Working dwell time feature
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
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24314e2361
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a4faeb28b0
35 changed files with 516 additions and 289 deletions
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@ -26,11 +26,17 @@ static bool StatusUpdateFlag = true;
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static Protocol::ReferenceSettings ref;
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static volatile uint64_t lastISR;
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static uint32_t IF1 = HW::DefaultIF1;
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static uint32_t IF2 = HW::DefaultIF2;
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static uint32_t ADCsamplerate = HW::DefaultADCSamplerate;
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static uint8_t ADCprescaler = HW::DefaultADCprescaler;
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static uint16_t DFTphaseInc = HW::DefaultDFTphaseInc;
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// increment when device config struct format changed. If a wrong version is found in flash, it will revert to default values
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static constexpr uint16_t deviceConfigVersion = 0x001;
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using DeviceConfig = struct _devicConfig {
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uint16_t version;
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Protocol::DeviceConfig config;
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uint32_t IF2;
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uint32_t ADCsamplerate;
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};
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static DeviceConfig deviceConfig;
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using namespace HWHAL;
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@ -100,6 +106,8 @@ bool HW::Init() {
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activeMode = Mode::Idle;
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LoadDeviceConfig();
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Si5351.Init();
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// Use Si5351 to generate reference frequencies for other PLLs and ADC
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@ -152,12 +160,12 @@ bool HW::Init() {
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FPGA::DisableHardwareOverwrite();
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// Set default ADC samplerate
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, ADCprescaler);
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, deviceConfig.config.V1.ADCprescaler);
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// Set phase increment according to
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, DFTphaseInc);
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, deviceConfig.config.V1.DFTphaseInc);
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// Set default settling time
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FPGA::SetSettlingTime(HW::DefaultDwellTime);
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FPGA::SetSettlingTime(deviceConfig.config.V1.PLLSettlingDelay);
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Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
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@ -190,7 +198,7 @@ bool HW::Init() {
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} else {
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LOG_INFO("LO1 VCO map complete");
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}
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LO1.SetFrequency(1000000000 + IF1);
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LO1.SetFrequency(1000000000 + deviceConfig.config.V1.IF1);
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LO1.UpdateFrequency();
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LOG_DEBUG("LO temp: %u", LO1.GetTemp());
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@ -428,37 +436,39 @@ Si5351C::PLLSource HW::Ref::getSource() {
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}
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}
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void HW::setAcquisitionFrequencies(Protocol::DeviceConfig s) {
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IF1 = s.V1.IF1;
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ADCprescaler = s.V1.ADCprescaler;
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DFTphaseInc = s.V1.DFTphaseInc;
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float ADCrate = (float) FPGA::Clockrate / ADCprescaler;
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IF2 = ADCrate * DFTphaseInc / 4096;
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ADCsamplerate = ADCrate;
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static void updateOtherParametersFromProtocolDeviceConfig() {
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float ADCrate = (float) FPGA::Clockrate / deviceConfig.config.V1.ADCprescaler;
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deviceConfig.IF2 = ADCrate * deviceConfig.config.V1.DFTphaseInc / 4096;
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deviceConfig.ADCsamplerate = ADCrate;
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}
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void HW::setDeviceConfig(Protocol::DeviceConfig s) {
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deviceConfig.config = s;
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if(deviceConfig.config.V1.PLLSettlingDelay < HW::MinPLLSettlingDelay) {
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deviceConfig.config.V1.PLLSettlingDelay = HW::MinPLLSettlingDelay;
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}
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updateOtherParametersFromProtocolDeviceConfig();
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SaveDeviceConfig();
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}
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Protocol::DeviceConfig HW::getDeviceConfig() {
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Protocol::DeviceConfig s;
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s.V1.ADCprescaler = ADCprescaler;
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s.V1.DFTphaseInc = DFTphaseInc;
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s.V1.IF1 = IF1;
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return s;
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return deviceConfig.config;
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}
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uint32_t HW::getIF1() {
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return IF1;
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return deviceConfig.config.V1.IF1;
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}
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uint32_t HW::getIF2() {
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return IF2;
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return deviceConfig.IF2;
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}
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uint32_t HW::getADCRate() {
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return ADCsamplerate;
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return deviceConfig.ADCsamplerate;
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}
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uint8_t HW::getADCPrescaler() {
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return ADCprescaler;
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return deviceConfig.config.V1.ADCprescaler;
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}
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uint64_t HW::getLastISRTimestamp() {
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@ -496,6 +506,44 @@ void HW::updateDeviceStatus() {
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}
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uint16_t HW::getDFTPhaseInc() {
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return DFTphaseInc;
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return deviceConfig.config.V1.DFTphaseInc;
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}
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uint8_t HW::getPLLSettlingDelay() {
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return deviceConfig.config.V1.PLLSettlingDelay;
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}
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bool HW::LoadDeviceConfig() {
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HWHAL::flash.read(flash_address, sizeof(deviceConfig), &deviceConfig);
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if(deviceConfig.version != deviceConfigVersion) {
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LOG_WARN("Invalid version in flash, expected %u, got %u", deviceConfigVersion, deviceConfig.version);
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SetDefaultDeviceConfig();
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return false;
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} else {
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LOG_INFO("Device config loaded from flash");
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return true;
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}
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}
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bool HW::SaveDeviceConfig() {
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if(!HWHAL::flash.eraseRange(flash_address, flash_size)) {
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return false;
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}
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uint32_t write_size = sizeof(deviceConfig);
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if(write_size % Flash::PageSize != 0) {
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// round up to next page
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write_size += Flash::PageSize - write_size % Flash::PageSize;
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}
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return HWHAL::flash.write(flash_address, write_size, &deviceConfig);
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}
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void HW::SetDefaultDeviceConfig() {
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memset(&deviceConfig, 0, sizeof(deviceConfig));
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deviceConfig.version = deviceConfigVersion;
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deviceConfig.config.V1.IF1 = HW::DefaultIF1;
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deviceConfig.config.V1.ADCprescaler = HW::DefaultADCprescaler;
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deviceConfig.config.V1.DFTphaseInc = HW::DefaultDFTphaseInc;
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deviceConfig.config.V1.PLLSettlingDelay = HW::DefaultPLLSettlingDelay;
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updateOtherParametersFromProtocolDeviceConfig();
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LOG_INFO("Device config set to default");
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}
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