Working dwell time feature

- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
This commit is contained in:
Jan Käberich 2025-01-03 14:36:10 +01:00
parent 24314e2361
commit a4faeb28b0
35 changed files with 516 additions and 289 deletions

View file

@ -353,7 +353,7 @@ void FPGA::SetMode(Mode mode) {
Low(AUX2);
Delay::us(1);
High(CS);
// Configure SPI to use faster speed of 32MHz
// Configure SPI to use faster speed of 42.5MHz
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_4;
break;
case Mode::SourcePLL:
@ -361,15 +361,15 @@ void FPGA::SetMode(Mode mode) {
Low(AUX2);
Delay::us(1);
High(AUX1);
// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_16;
break;
case Mode::LOPLL:
Low(CS);
Low(AUX1);
Delay::us(1);
High(AUX2);
// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
break;
}

View file

@ -1,5 +1,9 @@
#include "stm.hpp"
#define LOG_LEVEL LOG_LEVEL_INFO
#define LOG_MODULE "STM"
#include "Log.h"
using Callback = void(*)(void);
static constexpr uint8_t numCallbacks = 10;
static Callback callbacks[numCallbacks];
@ -34,6 +38,7 @@ bool STM::DispatchToInterrupt(void (*cb)(void)) {
return true;
} else {
// already at limit
LOG_ERR("Interrupt dispatch queue full");
return false;
}
}