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https://github.com/jankae/LibreVNA.git
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Working dwell time feature
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
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24314e2361
commit
a4faeb28b0
35 changed files with 516 additions and 289 deletions
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@ -353,7 +353,7 @@ void FPGA::SetMode(Mode mode) {
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Low(AUX2);
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Delay::us(1);
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High(CS);
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// Configure SPI to use faster speed of 32MHz
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// Configure SPI to use faster speed of 42.5MHz
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_4;
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break;
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case Mode::SourcePLL:
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@ -361,15 +361,15 @@ void FPGA::SetMode(Mode mode) {
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Low(AUX2);
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Delay::us(1);
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High(AUX1);
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// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
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// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_16;
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break;
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case Mode::LOPLL:
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Low(CS);
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Low(AUX1);
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Delay::us(1);
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High(AUX2);
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// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
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// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
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break;
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}
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@ -1,5 +1,9 @@
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#include "stm.hpp"
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "STM"
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#include "Log.h"
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using Callback = void(*)(void);
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static constexpr uint8_t numCallbacks = 10;
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static Callback callbacks[numCallbacks];
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@ -34,6 +38,7 @@ bool STM::DispatchToInterrupt(void (*cb)(void)) {
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return true;
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} else {
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// already at limit
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LOG_ERR("Interrupt dispatch queue full");
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return false;
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}
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}
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