mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-07 07:23:43 +00:00
Working dwell time feature
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
This commit is contained in:
Jan Käberich
parent
24314e2361
commit
a4faeb28b0
35 changed files with 516 additions and 289 deletions
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@ -273,7 +273,7 @@ inline void App_Process() {
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}
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break;
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case Protocol::PacketType::DeviceConfiguration:
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HW::setAcquisitionFrequencies(recv_packet.deviceConfig);
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HW::setDeviceConfig(recv_packet.deviceConfig);
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Communication::SendWithoutPayload(Protocol::PacketType::Ack);
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break;
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case Protocol::PacketType::SetTrigger:
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@ -216,7 +216,6 @@ using DeviceInfo = struct _deviceInfo {
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uint8_t limits_maxAmplitudePoints;
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uint64_t limits_maxFreqHarmonic;
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uint8_t num_ports;
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uint16_t limits_minDwellTime;
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uint16_t limits_maxDwellTime;
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};
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@ -440,6 +439,7 @@ using DeviceConfig = struct _deviceconfig {
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uint32_t IF1;
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uint8_t ADCprescaler;
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uint16_t DFTphaseInc;
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uint8_t PLLSettlingDelay;
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} V1;
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struct {
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uint32_t ip;
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@ -353,7 +353,7 @@ void FPGA::SetMode(Mode mode) {
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Low(AUX2);
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Delay::us(1);
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High(CS);
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// Configure SPI to use faster speed of 32MHz
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// Configure SPI to use faster speed of 42.5MHz
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_4;
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break;
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case Mode::SourcePLL:
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@ -361,15 +361,15 @@ void FPGA::SetMode(Mode mode) {
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Low(AUX2);
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Delay::us(1);
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High(AUX1);
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// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
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// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_16;
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break;
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case Mode::LOPLL:
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Low(CS);
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Low(AUX1);
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Delay::us(1);
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High(AUX2);
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// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
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// Configure SPI to use slower speed of 10.625MHz (MAX2871 is limited to 20MHz)
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FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
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break;
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}
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@ -1,5 +1,9 @@
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#include "stm.hpp"
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "STM"
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#include "Log.h"
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using Callback = void(*)(void);
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static constexpr uint8_t numCallbacks = 10;
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static Callback callbacks[numCallbacks];
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@ -34,6 +38,7 @@ bool STM::DispatchToInterrupt(void (*cb)(void)) {
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return true;
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} else {
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// already at limit
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LOG_ERR("Interrupt dispatch queue full");
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return false;
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}
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}
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@ -26,11 +26,17 @@ static bool StatusUpdateFlag = true;
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static Protocol::ReferenceSettings ref;
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static volatile uint64_t lastISR;
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static uint32_t IF1 = HW::DefaultIF1;
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static uint32_t IF2 = HW::DefaultIF2;
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static uint32_t ADCsamplerate = HW::DefaultADCSamplerate;
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static uint8_t ADCprescaler = HW::DefaultADCprescaler;
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static uint16_t DFTphaseInc = HW::DefaultDFTphaseInc;
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// increment when device config struct format changed. If a wrong version is found in flash, it will revert to default values
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static constexpr uint16_t deviceConfigVersion = 0x001;
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using DeviceConfig = struct _devicConfig {
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uint16_t version;
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Protocol::DeviceConfig config;
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uint32_t IF2;
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uint32_t ADCsamplerate;
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};
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static DeviceConfig deviceConfig;
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using namespace HWHAL;
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@ -100,6 +106,8 @@ bool HW::Init() {
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activeMode = Mode::Idle;
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LoadDeviceConfig();
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Si5351.Init();
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// Use Si5351 to generate reference frequencies for other PLLs and ADC
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@ -152,12 +160,12 @@ bool HW::Init() {
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FPGA::DisableHardwareOverwrite();
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// Set default ADC samplerate
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, ADCprescaler);
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, deviceConfig.config.V1.ADCprescaler);
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// Set phase increment according to
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, DFTphaseInc);
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, deviceConfig.config.V1.DFTphaseInc);
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// Set default settling time
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FPGA::SetSettlingTime(HW::DefaultDwellTime);
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FPGA::SetSettlingTime(deviceConfig.config.V1.PLLSettlingDelay);
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Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
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@ -190,7 +198,7 @@ bool HW::Init() {
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} else {
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LOG_INFO("LO1 VCO map complete");
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}
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LO1.SetFrequency(1000000000 + IF1);
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LO1.SetFrequency(1000000000 + deviceConfig.config.V1.IF1);
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LO1.UpdateFrequency();
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LOG_DEBUG("LO temp: %u", LO1.GetTemp());
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@ -428,37 +436,39 @@ Si5351C::PLLSource HW::Ref::getSource() {
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}
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}
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void HW::setAcquisitionFrequencies(Protocol::DeviceConfig s) {
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IF1 = s.V1.IF1;
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ADCprescaler = s.V1.ADCprescaler;
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DFTphaseInc = s.V1.DFTphaseInc;
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float ADCrate = (float) FPGA::Clockrate / ADCprescaler;
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IF2 = ADCrate * DFTphaseInc / 4096;
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ADCsamplerate = ADCrate;
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static void updateOtherParametersFromProtocolDeviceConfig() {
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float ADCrate = (float) FPGA::Clockrate / deviceConfig.config.V1.ADCprescaler;
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deviceConfig.IF2 = ADCrate * deviceConfig.config.V1.DFTphaseInc / 4096;
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deviceConfig.ADCsamplerate = ADCrate;
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}
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void HW::setDeviceConfig(Protocol::DeviceConfig s) {
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deviceConfig.config = s;
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if(deviceConfig.config.V1.PLLSettlingDelay < HW::MinPLLSettlingDelay) {
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deviceConfig.config.V1.PLLSettlingDelay = HW::MinPLLSettlingDelay;
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}
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updateOtherParametersFromProtocolDeviceConfig();
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SaveDeviceConfig();
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}
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Protocol::DeviceConfig HW::getDeviceConfig() {
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Protocol::DeviceConfig s;
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s.V1.ADCprescaler = ADCprescaler;
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s.V1.DFTphaseInc = DFTphaseInc;
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s.V1.IF1 = IF1;
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return s;
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return deviceConfig.config;
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}
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uint32_t HW::getIF1() {
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return IF1;
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return deviceConfig.config.V1.IF1;
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}
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uint32_t HW::getIF2() {
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return IF2;
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return deviceConfig.IF2;
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}
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uint32_t HW::getADCRate() {
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return ADCsamplerate;
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return deviceConfig.ADCsamplerate;
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}
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uint8_t HW::getADCPrescaler() {
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return ADCprescaler;
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return deviceConfig.config.V1.ADCprescaler;
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}
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uint64_t HW::getLastISRTimestamp() {
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@ -496,6 +506,44 @@ void HW::updateDeviceStatus() {
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}
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uint16_t HW::getDFTPhaseInc() {
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return DFTphaseInc;
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return deviceConfig.config.V1.DFTphaseInc;
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}
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uint8_t HW::getPLLSettlingDelay() {
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return deviceConfig.config.V1.PLLSettlingDelay;
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}
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bool HW::LoadDeviceConfig() {
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HWHAL::flash.read(flash_address, sizeof(deviceConfig), &deviceConfig);
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if(deviceConfig.version != deviceConfigVersion) {
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LOG_WARN("Invalid version in flash, expected %u, got %u", deviceConfigVersion, deviceConfig.version);
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SetDefaultDeviceConfig();
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return false;
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} else {
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LOG_INFO("Device config loaded from flash");
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return true;
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}
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}
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bool HW::SaveDeviceConfig() {
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if(!HWHAL::flash.eraseRange(flash_address, flash_size)) {
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return false;
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}
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uint32_t write_size = sizeof(deviceConfig);
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if(write_size % Flash::PageSize != 0) {
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// round up to next page
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write_size += Flash::PageSize - write_size % Flash::PageSize;
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}
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return HWHAL::flash.write(flash_address, write_size, &deviceConfig);
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}
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void HW::SetDefaultDeviceConfig() {
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memset(&deviceConfig, 0, sizeof(deviceConfig));
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deviceConfig.version = deviceConfigVersion;
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deviceConfig.config.V1.IF1 = HW::DefaultIF1;
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deviceConfig.config.V1.ADCprescaler = HW::DefaultADCprescaler;
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deviceConfig.config.V1.DFTphaseInc = HW::DefaultDFTphaseInc;
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deviceConfig.config.V1.PLLSettlingDelay = HW::DefaultPLLSettlingDelay;
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updateOtherParametersFromProtocolDeviceConfig();
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LOG_INFO("Device config set to default");
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}
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@ -45,7 +45,8 @@ static constexpr uint32_t BandSwitchFrequency = 25000000;
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static constexpr uint32_t DefaultLO2 = DefaultIF1 - DefaultIF2;
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static constexpr uint8_t LO2Multiplier = 13;
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static constexpr uint32_t SI5351CPLLAlignedFrequency = DefaultLO2 * LO2Multiplier;
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static constexpr uint16_t DefaultDwellTime = 60;
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static constexpr uint16_t DefaultPLLSettlingDelay = 60;
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static constexpr uint16_t MinPLLSettlingDelay = 10;
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static constexpr uint8_t DefaultADCprescaler = FPGA::Clockrate / DefaultADCSamplerate;
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static_assert(DefaultADCprescaler * DefaultADCSamplerate == FPGA::Clockrate, "ADCSamplerate can not be reached exactly");
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@ -87,7 +88,6 @@ static constexpr Protocol::DeviceInfo Info = {
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.limits_maxAmplitudePoints = Cal::maxPoints,
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.limits_maxFreqHarmonic = 18000000000,
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.num_ports = 2,
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.limits_minDwellTime = 0,
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.limits_maxDwellTime = 10239,
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};
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@ -135,13 +135,21 @@ namespace Ref {
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Si5351C::PLLSource getSource();
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}
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// Acquisition frequency settings
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void setAcquisitionFrequencies(Protocol::DeviceConfig s);
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// Device configuration settings
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constexpr uint32_t flash_address = Firmware::maxSize + Cal::flash_size; // stored directly behind calibration in flash
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constexpr uint32_t flash_size = 4096; // reserve one sector for now
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bool LoadDeviceConfig();
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bool SaveDeviceConfig();
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void SetDefaultDeviceConfig();
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void setDeviceConfig(Protocol::DeviceConfig s);
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Protocol::DeviceConfig getDeviceConfig();
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uint32_t getIF1();
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uint32_t getIF2();
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uint32_t getADCRate();
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uint8_t getADCPrescaler();
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uint16_t getDFTPhaseInc();
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uint8_t getPLLSettlingDelay();
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}
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@ -47,7 +47,8 @@ static_assert(alternativePhaseInc * alternativeSamplerate == 4096 * HW::DefaultI
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// Constants for USB buffer overflow prevention
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static constexpr uint16_t maxPointsBetweenHalts = 40;
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static constexpr uint32_t reservedUSBbuffer = maxPointsBetweenHalts * (sizeof(Protocol::Datapoint) + 8 /*USB packet overhead*/);
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static constexpr uint16_t full2portDatapointSize = 66;// See Protocol::VNADatapoint::
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static constexpr uint32_t reservedUSBbuffer = (maxPointsBetweenHalts + 2 /*additional buffer*/) * (full2portDatapointSize + 8 /*USB packet overhead*/);
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using namespace HWHAL;
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@ -118,6 +119,9 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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if(settings.points > FPGA::MaxPoints) {
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settings.points = FPGA::MaxPoints;
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}
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if(settings.dwell_time > HW::Info.limits_maxDwellTime) {
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settings.dwell_time = HW::Info.limits_maxDwellTime;
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}
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settings = s;
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// calculate factor between adjacent points for log sweep for faster calculation when sweeping
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logMultiplier = pow((double) settings.f_stop / settings.f_start, 1.0 / (settings.points-1));
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@ -132,7 +136,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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// has to be one less than actual number of samples
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FPGA::SetSamplesPerPoint(samplesPerPoint);
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FPGA::SetSettlingTime(s.dwell_time);
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FPGA::SetSettlingTime(s.dwell_time + HW::getPLLSettlingDelay());
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// reset unlevel flag if it was set from a previous sweep/mode
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HW::SetOutputUnlevel(false);
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@ -216,6 +220,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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pointsWithoutHalt++;
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if(pointsWithoutHalt > maxPointsBetweenHalts) {
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needs_halt = true;
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pointsWithoutHalt = 0;
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}
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} else {
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pointsWithoutHalt = 0;
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@ -304,7 +309,9 @@ static void PassOnData() {
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Protocol::PacketInfo info;
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info.type = Protocol::PacketType::VNADatapoint;
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info.VNAdatapoint = &data;
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Communication::Send(info);
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if(!Communication::Send(info)) {
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LOG_ERR("Failed to transmit VNADatapoint");
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}
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data.clear();
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}
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