Working dwell time feature

- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles

Software/PC_Application/LibreVNA-GUI/Traces/Math/expression.cpp

@@ -142,6 +142,6 @@ void Math::Expression::expressionChanged()
         break;
     }
     if(input) {
-        inputSamplesChanged(0, input->getData().size());
+        inputSamplesChanged(0, input->numSamples());
     }
 }