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Working dwell time feature
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
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35 changed files with 516 additions and 289 deletions
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@ -147,7 +147,7 @@ void Math::DFT::inputSamplesChanged(unsigned int begin, unsigned int end)
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{
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Q_UNUSED(begin);
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Q_UNUSED(end);
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if(input->getData().size() < 2) {
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if(input->numSamples() < 2) {
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// not enough input data
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clearOutput();
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warning("Not enough input samples");
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@ -161,7 +161,7 @@ void Math::DFT::inputSamplesChanged(unsigned int begin, unsigned int end)
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void Math::DFT::updateDFT()
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{
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if(dataType != DataType::Invalid) {
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inputSamplesChanged(0, input->getData().size());
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inputSamplesChanged(0, input->numSamples());
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}
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}
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