Working dwell time feature

- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
This commit is contained in:
Jan Käberich 2025-01-03 14:36:10 +01:00
parent 24314e2361
commit a4faeb28b0
35 changed files with 516 additions and 289 deletions

View file

@ -147,7 +147,7 @@ void Math::DFT::inputSamplesChanged(unsigned int begin, unsigned int end)
{
Q_UNUSED(begin);
Q_UNUSED(end);
if(input->getData().size() < 2) {
if(input->numSamples() < 2) {
// not enough input data
clearOutput();
warning("Not enough input samples");
@ -161,7 +161,7 @@ void Math::DFT::inputSamplesChanged(unsigned int begin, unsigned int end)
void Math::DFT::updateDFT()
{
if(dataType != DataType::Invalid) {
inputSamplesChanged(0, input->getData().size());
inputSamplesChanged(0, input->numSamples());
}
}